aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/dma/imx-sdma.c
Commit message (Collapse)AuthorAgeFilesLines
* Merge branch 'imx' into dmaengine-fixesDan Williams2011-02-141-35/+41
|\
| * Merge branch 'dmaengine-shawn' into dmaengineSascha Hauer2011-01-311-10/+6
| |\
| | * dmaengine: imx-sdma: fix up param for the last BD in sdma_prep_slave_sg()Shawn Guo2011-01-311-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the reference manual, bit "L" should be set while bit "C" should be cleared for the last buffer descriptor in the non-cyclic chain, so that sdma can stop trying to find the next BD and end the transfer. In case of sdma_prep_slave_sg(), BD_LAST needs to be set and BD_CONT be cleared for the last BD. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * dmaengine: imx-sdma: correct sdmac->status in sdma_handle_channel_loop()Shawn Guo2011-01-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | sdma_handle_channel_loop() is the handler of cyclic tx. One period success does not really mean the success of the tx. Instead of DMA_SUCCESS, DMA_IN_PROGRESS should be the one to tell. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * dmaengine: imx-sdma: return sdmac->status in sdma_tx_status()Shawn Guo2011-01-311-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The sdmac->status was designed to reflect the status of the tx, so simply return it in sdma_tx_status(). Then dma client can call dma_async_is_tx_complete() to know the status of the tx. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * dmaengine: imx-sdma: set sdmac->status to DMA_ERROR in err_out of ↵Shawn Guo2011-01-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sdma_prep_slave_sg() sdma_prep_dma_cyclic() sets sdmac->status to DMA_ERROR in err_out, and sdma_prep_slave_sg() needs to do the same. Otherwise, sdmac->status stays at DMA_IN_PROGRESS, which will make the function return immediately next time it gets called. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * dmaengine: imx-sdma: remove IMX_DMA_SG_LOOP handling in sdma_prep_slave_sg()Shawn Guo2011-01-311-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a leftover from the time that the driver did not have sdma_prep_dma_cyclic callback and implemented sound dma as a looped sg chain. And it can be removed now. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | dmaengine i.MX SDMA: reserve channel 0 by not registering itSascha Hauer2011-01-311-18/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need channel 0 of the sdma engine for internal purposes. We accomplished this by calling dma_request_channel() in the probe function. This does not work when multiple dma engines are present which is the case when IPU support for i.MX31/35 is compiled in. So instead of registering channel 0 and reserving it afterwards simply do not register it in the first place. With this the dmaengine channel counting does not match sdma channel counting anymore, so we have to use sdma channel counting in the driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | dmaengine i.MX SDMA: initialize dma capabilities outside channel loopSascha Hauer2011-01-311-3/+3
| | | | | | | | | | | | | | | | | | The capabilities are device specific fields, not channel specific fields. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | dmaengine i.MX SDMA: do not initialize chan_id fieldSascha Hauer2011-01-311-1/+0
| | | | | | | | | | | | | | | | | | This is bogus as the dmaengine core will overwrite this field. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | dmaengine i.MX sdma: check sg entries for valid addresses and lengthsSascha Hauer2011-01-311-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch lets sdma_prep_slave_sg fail if the entries of an sg list do not start on multiples of the word size or if the lengths are not multiple of the word size. Also, catch the previously unhandled DMA_SLAVE_BUSWIDTH_8_BYTES and DMA_SLAVE_BUSWIDTH_UNDEFINED cases. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | dmaengine i.MX sdma: set maximum segment size for our deviceSascha Hauer2011-01-311-0/+3
| |/ | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | dmaengine: imx-sdma: fix inconsistent naming in sdma_assign_cookie()Shawn Guo2011-01-291-4/+4
| | | | | | | | | | | | | | | | | | Variable name sdma and sdmac are consistently used as the pointer to sdma_engine and sdma_channel respectively throughout the file. The patch fixes the inconsistency seen in function sdma_assign_cookie(). Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | dmaengine: imx-sdma: propagate error in sdma_probe() instead of returning 0Shawn Guo2011-01-291-1/+1
| | | | | | | | | | | | Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | dmaengine i.MX SDMA: Fix firmware loadingSascha Hauer2011-01-291-1/+1
|/ | | | | | | | | | | When loading the microcode to the SDMA engine we have to use the ram_code_start_addr found in the firmware image. The copy in the sdma engine is not initialized correctly. This is broken since: 5b28aa3 dmaengine i.MX SDMA: Allow to run without firmware Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into ↵Russell King2011-01-051-96/+78
|\ | | | | | | devel-stable
| * dmaengine i.MX SDMA: Allow to run without firmwareSascha Hauer2010-12-031-96/+78
| | | | | | | | | | | | | | | | | | | | | | | | The SDMA firmware consists of a ROM part and a RAM part. The ROM part is always present in the SDMA engine and is sufficient for many cases. This patch allows to pass in platform data containing the script addresses in ROM, so loading a firmware is optional now. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Dan Williams <dan.j.williams@intel.com>
* | dmaengine i.MX SDMA: initialize on module_initSascha Hauer2010-12-071-1/+1
| | | | | | | | | | | | | | | | The firmware framework gets initialized during fs_initcall time, so we are not allowed to call request_firmware earlier. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | dmaengine: imx-sdma: fix bug in buffer descriptor initializationAnatolij Gustschin2010-12-041-1/+1
|/ | | | | | | | | | | | | | | | | | | Currently while submitting scatterlists with more than one SG entry the DMA buffer address from the first SG entry is inserted into all initialized DMA buffer descriptors. This is due to the typo in the for_each_sg() loop where the scatterlist pointer is used for obtaining the DMA buffer address and _not_ the SG list iterator. As a result all received data will be written only into the first DMA buffer while reading. While writing the data from the first DMA buffer is send to the device multiple times. This caused the filesystem destruction on the MMC card when using DMA in mxcmmc driver. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* dmaengine: Add Freescale i.MX SDMA supportSascha Hauer2010-10-051-0/+1392
This patch adds support for the Freescale i.MX SDMA engine. The SDMA engine is a scatter/gather DMA engine which is implemented as a seperate coprocessor. SDMA needs its own firmware which is requested using the standard request_firmware mechanism. The firmware has different entry points for each peripheral type, so drivers have to pass the peripheral type to the DMA engine which in turn picks the correct firmware entry point from a table contained in the firmware image itself. The original Freescale code also supports support for transfering data to the internal SRAM which needs different entry points to the firmware. Support for this is currently not implemented. Also, support for the ASRC (asymmetric sample rate converter) is skipped. I took a very simple approach to implement dmaengine support. Only a single descriptor is statically assigned to a each channel. This means that transfers can't be queued up but only a single transfer is in progress. This simplifies implementation a lot and is sufficient for the usual device/memory transfers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Linus Walleij <linus.ml.walleij@gmail.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
generated by cgit v1.1 at 2024-12-26 02:15:37 +0000