aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorHiroshi DOYU <Hiroshi.DOYU@nokia.com>2009-09-24 16:23:10 -0700
committerTony Lindgren <tony@atomide.com>2009-09-24 16:23:10 -0700
commit8828880d09e4466ad6b357a31fdd242594c7b111 (patch)
tree6ed4e5babf1b5501cd2a3fe51dd119a878d06b44
parent1ffe627dcfce820b316ee520c58fca54550a18ee (diff)
downloadkernel_samsung_tuna-8828880d09e4466ad6b357a31fdd242594c7b111.zip
kernel_samsung_tuna-8828880d09e4466ad6b357a31fdd242594c7b111.tar.gz
kernel_samsung_tuna-8828880d09e4466ad6b357a31fdd242594c7b111.tar.bz2
omap: mailbox: Flush posted write when acking mailbox irq
The only way to flush posted write to L4 bus is to do a read back of the same register right after the write. This seems to be mostly needed in interrupt handlers to avoid causing spurious interrupts. The earlier fix has been to mark the L4 bus as strongly ordered memory, which solves the problem, but causes performance penalties. Similar to the fix, 03803a71041e3bc3c077f4e7b92f6ceaa9426df3 Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/mach-omap2/mailbox.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 5bf9a2f..f3fefca 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -176,6 +176,9 @@ static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
mbox_write_reg(bit, p->irqstatus);
+
+ /* Flush posted write for irq status to avoid spurious interrupts */
+ mbox_read_reg(p->irqstatus);
}
static int omap2_mbox_is_irq(struct omap_mbox *mbox,