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| author | Thiemo Seufer <ths@networkno.de> | 2007-09-05 17:44:50 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 23:46:03 +0100 |
| commit | bcb0fd94633afde9c1f4f8aca43141ba2c78f04b (patch) | |
| tree | 690cb6b8f61e05eaa50ea36ce809507fbacdf1ae | |
| parent | 7ca16d269a1a4b96d98968b48f137977bcab1522 (diff) | |
| download | kernel_samsung_tuna-bcb0fd94633afde9c1f4f8aca43141ba2c78f04b.zip kernel_samsung_tuna-bcb0fd94633afde9c1f4f8aca43141ba2c78f04b.tar.gz kernel_samsung_tuna-bcb0fd94633afde9c1f4f8aca43141ba2c78f04b.tar.bz2 | |
[MIPS] Define known MIPS ISA overrides for Sibyte and Excite boards.
Signed-Off-By: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | include/asm-mips/mach-excite/cpu-feature-overrides.h | 5 | ||||
| -rw-r--r-- | include/asm-mips/mach-sibyte/cpu-feature-overrides.h | 7 |
2 files changed, 11 insertions, 1 deletions
diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h index 07f4322..107104c 100644 --- a/include/asm-mips/mach-excite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h @@ -34,6 +34,11 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h index 63d5bf6..1c1f924 100644 --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h @@ -9,7 +9,7 @@ #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H /* - * Sibyte are MIPS64 processors weired to a specific configuration + * Sibyte are MIPS64 processors wired to a specific configuration */ #define cpu_has_watch 1 #define cpu_has_mips16 0 @@ -33,6 +33,11 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 1 +#define cpu_has_mips64r2 0 + #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 |