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| author | Tony Lofthouse <a0741364@ti.com> | 2011-06-22 14:28:27 -0700 |
|---|---|---|
| committer | Iliyan Malchev <malchev@google.com> | 2011-06-23 18:08:46 -0700 |
| commit | d98534b8f865dbd1b1fbdfeb01276ed640d87e4d (patch) | |
| tree | 113dfd80ed03e763239d99afe96c8b5afd64ebe4 | |
| parent | 61bff33dd4bf9aa1ef04f13beb351045efb99455 (diff) | |
| download | kernel_samsung_tuna-d98534b8f865dbd1b1fbdfeb01276ed640d87e4d.zip kernel_samsung_tuna-d98534b8f865dbd1b1fbdfeb01276ed640d87e4d.tar.gz kernel_samsung_tuna-d98534b8f865dbd1b1fbdfeb01276ed640d87e4d.tar.bz2 | |
(TEMP) PVR-KM: Allow tiler memory to be wrapped
OSAcquirePhysPageAddr assumed that a given virtual address would
map to a page frame number corresponding to memory/ram in the kernel.
For tiler memory this assumption would fail as the mapping would be to
the tiler virtual address space.
This change adjusts this assumption.
Signed-off-by: Iliyan Malchev <malchev@google.com>
| -rw-r--r-- | drivers/gpu/pvr/Makefile | 3 | ||||
| -rw-r--r-- | drivers/gpu/pvr/osfunc.c | 54 |
2 files changed, 55 insertions, 2 deletions
diff --git a/drivers/gpu/pvr/Makefile b/drivers/gpu/pvr/Makefile index eabdcce..32b8ece 100644 --- a/drivers/gpu/pvr/Makefile +++ b/drivers/gpu/pvr/Makefile @@ -39,7 +39,8 @@ ccflags-y += \ -DPVR_LDM_DRIVER_REGISTRATION_NAME="\"pvrsrvkm\"" \ -DPVRSRV_FLUSH_KERNEL_OPS_LAST_ONLY \ -DPVRSRV_DO_NOT_FLUSH_CLIENT_OPS \ - -Idrivers/gpu/pvr/sgx + -Idrivers/gpu/pvr/sgx \ + -DSUPPORT_OMAP_TILER ccflags-$(CONFIG_PVR_SGXCORE_540) += \ -DSGX540 -DSUPPORT_SGX540 \ diff --git a/drivers/gpu/pvr/osfunc.c b/drivers/gpu/pvr/osfunc.c index 6abfff7..893af34 100644 --- a/drivers/gpu/pvr/osfunc.c +++ b/drivers/gpu/pvr/osfunc.c @@ -2265,6 +2265,47 @@ static IMG_BOOL CPUVAddrToPFN(struct vm_area_struct *psVMArea, IMG_UINT32 ulCPUV #endif } +#if defined(SUPPORT_OMAP_TILER) +static IMG_BOOL CPUAddrToTilerPhy(IMG_UINT32 vma, IMG_UINT32 *phyAddr) +{ + IMG_UINT32 tmpPhysAddr = 0; + pgd_t *pgd = NULL; + pmd_t *pmd = NULL; + pte_t *ptep = NULL, pte = 0x0; + IMG_BOOL bRet = IMG_FALSE; + + pgd = pgd_offset(current->mm, vma); + if (!(pgd_none(*pgd) || pgd_bad(*pgd))) + { + pmd = pmd_offset(pgd, vma); + if (!(pmd_none(*pmd) || pmd_bad(*pmd))) + { + ptep = pte_offset_map(pmd, vma); + if (ptep) + { + pte = *ptep; + if (pte_present(pte)) + { + tmpPhysAddr = (pte & PAGE_MASK) | + (~PAGE_MASK & vma); + bRet = IMG_TRUE; + } + } + } + } + /* If the physAddr is not in the TILER physical range + * then we don't proceed. */ + if ((tmpPhysAddr < 0x60000000) && (tmpPhysAddr > 0x7fffffff)) + { + PVR_DPF((PVR_DBG_ERROR, "CPUAddrToTilerPhy: Not in tiler range")); + tmpPhysAddr = 0; + bRet = IMG_FALSE; + } + *phyAddr = tmpPhysAddr; + return bRet; +} +#endif /* SUPPORT_OMAP_TILER */ + PVRSRV_ERROR OSReleasePhysPageAddr(IMG_HANDLE hOSWrapMem) { sWrapMemInfo *psInfo = (sWrapMemInfo *)hOSWrapMem; @@ -2529,7 +2570,18 @@ PVRSRV_ERROR OSAcquirePhysPageAddr(IMG_VOID *pvCPUVAddr, } if (psInfo->ppsPages[i] == NULL) { - +#if defined(SUPPORT_OMAP_TILER) + IMG_UINT32 tilerAddr; + /* This could be tiler memory.*/ + if (CPUAddrToTilerPhy(ulAddr, &tilerAddr)) + { + bHavePageStructs = IMG_TRUE; + psInfo->iNumPagesMapped++; + psInfo->psPhysAddr[i].uiAddr = tilerAddr; + psSysPAddr[i].uiAddr = tilerAddr; + continue; + } +#endif /* SUPPORT_OMAP_TILER */ bHaveNoPageStructs = IMG_TRUE; #if defined(VM_PFNMAP) |