diff options
| author | Jack Steiner <steiner@sgi.com> | 2009-09-03 12:56:02 -0500 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2009-09-09 14:05:24 -0700 |
| commit | fa526d0d641b5365676a1fb821ce359e217c9b85 (patch) | |
| tree | fa08cded30f46df90fe103a750f412e306f2d53e | |
| parent | a269cca9926faf8e44b340b017be0d884203141b (diff) | |
| download | kernel_samsung_tuna-fa526d0d641b5365676a1fb821ce359e217c9b85.zip kernel_samsung_tuna-fa526d0d641b5365676a1fb821ce359e217c9b85.tar.gz kernel_samsung_tuna-fa526d0d641b5365676a1fb821ce359e217c9b85.tar.bz2 | |
x86, pat: Fix cacheflush address in change_page_attr_set_clr()
Fix address passed to cpa_flush_range() when changing page
attributes from WB to UC. The address (*addr) is
modified by __change_page_attr_set_clr(). The result is that
the pages being flushed start at the _end_ of the changed range
instead of the beginning.
This should be considered for 2.6.30-stable and 2.6.31-stable.
Signed-off-by: Jack Steiner <steiner@sgi.com>
Acked-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cc: Stable team <stable@kernel.org>
| -rw-r--r-- | arch/x86/mm/pageattr.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index 7e600c1..e245775 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c @@ -822,6 +822,7 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages, { struct cpa_data cpa; int ret, cache, checkalias; + unsigned long baddr = 0; /* * Check, if we are requested to change a not supported @@ -853,6 +854,11 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages, */ WARN_ON_ONCE(1); } + /* + * Save address for cache flush. *addr is modified in the call + * to __change_page_attr_set_clr() below. + */ + baddr = *addr; } /* Must avoid aliasing mappings in the highmem code */ @@ -900,7 +906,7 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages, cpa_flush_array(addr, numpages, cache, cpa.flags, pages); } else - cpa_flush_range(*addr, numpages, cache); + cpa_flush_range(baddr, numpages, cache); } else cpa_flush_all(cache); |