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author | Ben Dooks <ben@simtec.co.uk> | 2009-07-30 23:23:41 +0100 |
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committer | Ben Dooks <ben-linux@fluff.org> | 2009-07-30 23:22:55 +0100 |
commit | dfff4e95d749c414af3f7350835139103408a50d (patch) | |
tree | f5a43849796c66ccb42fae6ab59e1240c403bfe5 /Documentation/arm | |
parent | ad78759529be38d6aa062233b980095cf74aa7f0 (diff) | |
download | kernel_samsung_tuna-dfff4e95d749c414af3f7350835139103408a50d.zip kernel_samsung_tuna-dfff4e95d749c414af3f7350835139103408a50d.tar.gz kernel_samsung_tuna-dfff4e95d749c414af3f7350835139103408a50d.tar.bz2 |
ARM: S3C: CPUFREQ: Add documentation for system
Add documentation for the S3C24XX style CPUFREQ driver.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'Documentation/arm')
-rw-r--r-- | Documentation/arm/Samsung-S3C24XX/CPUfreq.txt | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/Documentation/arm/Samsung-S3C24XX/CPUfreq.txt b/Documentation/arm/Samsung-S3C24XX/CPUfreq.txt new file mode 100644 index 0000000..76b3a11 --- /dev/null +++ b/Documentation/arm/Samsung-S3C24XX/CPUfreq.txt @@ -0,0 +1,75 @@ + S3C24XX CPUfreq support + ======================= + +Introduction +------------ + + The S3C24XX series support a number of power saving systems, such as + the ability to change the core, memory and peripheral operating + frequencies. The core control is exported via the CPUFreq driver + which has a number of different manual or automatic controls over the + rate the core is running at. + + There are two forms of the driver depending on the specific CPU and + how the clocks are arranged. The first implementation used as single + PLL to feed the ARM, memory and peripherals via a series of dividers + and muxes and this is the implementation that is documented here. A + newer version where there is a seperate PLL and clock divider for the + ARM core is available as a seperate driver. + + +Layout +------ + + The code core manages the CPU specific drivers, any data that they + need to register and the interface to the generic drivers/cpufreq + system. Each CPU registers a driver to control the PLL, clock dividers + and anything else associated with it. Any board that wants to use this + framework needs to supply at least basic details of what is required. + + The core registers with drivers/cpufreq at init time if all the data + necessary has been supplied. + + +CPU support +----------- + + The support for each CPU depends on the facilities provided by the + SoC and the driver as each device has different PLL and clock chains + associated with it. + + +Slow Mode +--------- + + The SLOW mode where the PLL is turned off altogether and the + system is fed by the external crystal input is currently not + supported. + + +sysfs +----- + + The core code exports extra information via sysfs in the directory + devices/system/cpu/cpu0/arch-freq. + + +Board Support +------------- + + Each board that wants to use the cpufreq code must register some basic + information with the core driver to provide information about what the + board requires and any restrictions being placed on it. + + The board needs to supply information about whether it needs the IO bank + timings changing, any maximum frequency limits and information about the + SDRAM refresh rate. + + + + +Document Author +--------------- + +Ben Dooks, Copyright 2009 Simtec Electronics +Licensed under GPLv2 |