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authorTodd Poynor <toddpoynor@google.com>2012-04-19 16:17:42 -0700
committerTodd Poynor <toddpoynor@google.com>2012-04-19 16:17:42 -0700
commit4cd5ca7677c762cf6fb649211d8a7e546e1e6a8b (patch)
treec067da7e71964f6fa475ac92faf0cd28818f6e9a /arch/arm/Kconfig
parent635aaea87060186666212363e26acc5207873b32 (diff)
parent84c606de0617ba304bca456f0ad06729198a5333 (diff)
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Merge linux-omap-3.0 into android-omap-3.0
Change-Id: I86dcae86b15baab2cb26e2c53faafb57c606a2b5 Signed-off-by: Todd Poynor <toddpoynor@google.com>
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r--arch/arm/Kconfig14
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9959144..dc73e61 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1180,7 +1180,7 @@ config ARM_ERRATA_743622
depends on CPU_V7
help
This option enables the workaround for the 743622 Cortex-A9
- (r2p0..r2p2) erratum. Under very rare conditions, a faulty
+ (r2p*) erratum. Under very rare conditions, a faulty
optimisation in the Cortex-A9 Store Buffer may lead to data
corruption. This workaround sets a specific bit in the diagnostic
register of the Cortex-A9 which disables the Store Buffer
@@ -1313,6 +1313,18 @@ config ARM_ERRATA_764369
relevant cache maintenance functions and sets a specific bit
in the diagnostic control register of the SCU.
+config PL310_ERRATA_769419
+ bool "PL310 errata: no automatic Store Buffer drain"
+ depends on CACHE_L2X0
+ help
+ On revisions of the PL310 prior to r3p2, the Store Buffer does
+ not automatically drain. This can cause normal, non-cacheable
+ writes to be retained when the memory system is idle, leading
+ to suboptimal I/O performance for drivers using coherent DMA.
+ This option adds a write barrier to the cpu_idle loop so that,
+ on systems with an outer cache, the store buffer is drained
+ explicitly.
+
endmenu
menu "Kernel Features"