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| author | Colin Cross <ccross@android.com> | 2011-09-14 15:59:50 -0700 |
|---|---|---|
| committer | Colin Cross <ccross@android.com> | 2011-09-19 23:35:45 -0700 |
| commit | 5ea3a7c6c63a2d9a5abc569696fb9d3e82a31c8d (patch) | |
| tree | 1c29d3754514af5108017ba7ae4c97e8f5bab5cb /arch/arm/include/asm | |
| parent | 5cd52e05024319101e86e948f6c1983cb4d3c496 (diff) | |
| download | kernel_samsung_tuna-5ea3a7c6c63a2d9a5abc569696fb9d3e82a31c8d.zip kernel_samsung_tuna-5ea3a7c6c63a2d9a5abc569696fb9d3e82a31c8d.tar.gz kernel_samsung_tuna-5ea3a7c6c63a2d9a5abc569696fb9d3e82a31c8d.tar.bz2 | |
ARM: cache-l2x0: update workaround for PL310 errata 727915
ARM errata 727915 for PL310 has been updated to include a new
workaround required for PL310 r2p0 for l2x0_flush_all, which also
affects l2x0_clean_all in my testing. For r2p0, clean or flush
each set/way individually. For r3p0 or greater, use the debug
register for cleaning and flushing.
Requires exporting the cache_id, sets and ways detected in the
init function for later use.
Change-Id: I215055cbe5dc7e4e8184fb2befc4aff672ef0a12
Signed-off-by: Colin Cross <ccross@android.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/hardware/cache-l2x0.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 16bd480..b3dd3bf 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -57,6 +57,7 @@ #define L2X0_STNDBY_MODE_EN (1 << 0) /* Registers shifts and masks */ +#define L2X0_CACHE_ID_REV_MASK (0x3f) #define L2X0_CACHE_ID_PART_MASK (0xf << 6) #define L2X0_CACHE_ID_PART_L210 (1 << 6) #define L2X0_CACHE_ID_PART_L310 (3 << 6) @@ -72,6 +73,8 @@ #define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 +#define REV_PL310_R2P0 4 + #ifndef __ASSEMBLY__ extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); #endif |