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| author | Nishanth Menon <nm@ti.com> | 2011-10-19 06:04:57 -0500 |
|---|---|---|
| committer | Todd Poynor <toddpoynor@google.com> | 2011-11-14 14:04:38 -0800 |
| commit | eba67332ad772d0a7be18372ef21d656c6fd70f7 (patch) | |
| tree | 6799e3e274659bf00ffbed603c3661e3f053ac3b /arch/arm/mach-omap2/include/mach | |
| parent | 47b6a6272945e425520223ade52e65936d02e85a (diff) | |
| download | kernel_samsung_tuna-eba67332ad772d0a7be18372ef21d656c6fd70f7.zip kernel_samsung_tuna-eba67332ad772d0a7be18372ef21d656c6fd70f7.tar.gz kernel_samsung_tuna-eba67332ad772d0a7be18372ef21d656c6fd70f7.tar.bz2 | |
OMAP4+: EMIF: remove duplicate overwrite of pwr shadow reg
We have a spurious shadow register overwrite which could create
miniscule window where the shadow register has values not expected
Change-Id: Ib8101e484240f1d0464f42704a14fddc21a6cab5
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/include/mach')
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/emif.h | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/arch/arm/mach-omap2/include/mach/emif.h b/arch/arm/mach-omap2/include/mach/emif.h index a29c5e7..30b2f71 100644 --- a/arch/arm/mach-omap2/include/mach/emif.h +++ b/arch/arm/mach-omap2/include/mach/emif.h @@ -166,29 +166,6 @@ #define DPD_DISABLE 0 #define DPD_ENABLE 1 -/* Maximum delay before Low Power Modes */ -#define REG_CS_TIM 0xF -#define REG_SR_TIM 0xF -#define REG_PD_TIM 0xF - -/* EMIF_PWR_MGMT_CTRL register */ -#define EMIF_PWR_MGMT_CTRL (\ - ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\ - ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\ - ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\ - ((LP_MODE_SELF_REFRESH << OMAP44XX_REG_LP_MODE_SHIFT)\ - & OMAP44XX_REG_LP_MODE_MASK) |\ - ((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\ - & OMAP44XX_REG_DPD_EN_MASK))\ - -#define EMIF_PWR_MGMT_CTRL_SHDW (\ - ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\ - & OMAP44XX_REG_CS_TIM_SHDW_MASK) |\ - ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\ - & OMAP44XX_REG_SR_TIM_SHDW_MASK) |\ - ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\ - & OMAP44XX_REG_PD_TIM_SHDW_MASK)) - /* * Value of bits 12:31 of DDR_PHY_CTRL_1 register: * All these fields have magic values dependent on frequency and |