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author | Aneesh V <aneesh@ti.com> | 2011-06-28 11:34:34 -0500 |
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committer | Nishanth Menon <nm@ti.com> | 2011-06-29 13:31:01 -0700 |
commit | 31e972b0df4c97226045edb8938eb8d98775a957 (patch) | |
tree | 5a79fcd6873c10583d39b8f93d47967abe9fb6d6 /arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |
parent | fc1dec3f80bdf1c9c184079aabbee0d0145f6520 (diff) | |
download | kernel_samsung_tuna-31e972b0df4c97226045edb8938eb8d98775a957.zip kernel_samsung_tuna-31e972b0df4c97226045edb8938eb8d98775a957.tar.gz kernel_samsung_tuna-31e972b0df4c97226045edb8938eb8d98775a957.tar.bz2 |
OMAP4: Add EMIF driver support
This patch adds EMIF driver registration support with hwmod.
This patch adds auto-generated header files for EMIF and
DMM IP blocks. The scripts are updated accordingly
We now have a set of APIs for:
Add a set of APIs for the following:
1. Calculating the values of emif configuration registers based on the
organization of memory in the device, the AC timing parameters of the
memory device, data from JESD209-2 - the LPDDR2 spec, and the frequency
at which the LPDDR2 interface is operating.
2. Updating the EMIF settings on:
a. frequency change
b. voltage ramp
c. temperature change
OMAP4 EMIF driver also supports the lppddr2 thermal management support as
expected by JEDEC standards.
[girishsg@ti.com: Helped in fixing the comments]
Signed-off-by: Girish S G <girishsg@ti.com>
[vvardhan@ti.com: contributed towards thermal support]
Signed-off-by: Vibhore Vardhan <vvardhan@ti.com>
[b-cousson@ti.com, santosh.shilimkar@ti.com: contributed for hwmod and basic
driver support, Thermal]
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_44xx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 106 |
1 files changed, 106 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 22a45f8..d0b9856 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -2093,6 +2093,108 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { }; /* + * 'emif' class + * external memory interface no1 + */ + +static struct omap_hwmod_class omap44xx_emif_hwmod_class = { + .name = "emif", +}; + +/* emif1 */ +static struct omap_hwmod omap44xx_emif1_hwmod; +static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { + { .irq = 110 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { + { + .pa_start = 0x4c000000, + .pa_end = 0x4c0000ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* emif_fw -> emif1 */ +static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { + .master = &omap44xx_emif_fw_hwmod, + .slave = &omap44xx_emif1_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_emif1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_emif1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* emif1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_emif1_slaves[] = { + &omap44xx_emif_fw__emif1, +}; + +static struct omap_hwmod omap44xx_emif1_hwmod = { + .name = "emif1", + .class = &omap44xx_emif_hwmod_class, + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_emif1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_emif1_irqs), + .main_clk = "emif1_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, + }, + }, + .slaves = omap44xx_emif1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_emif1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), +}; + +/* emif2 */ +static struct omap_hwmod omap44xx_emif2_hwmod; +static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { + { .irq = 111 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { + { + .pa_start = 0x4d000000, + .pa_end = 0x4d0000ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* emif_fw -> emif2 */ +static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { + .master = &omap44xx_emif_fw_hwmod, + .slave = &omap44xx_emif2_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_emif2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_emif2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* emif2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_emif2_slaves[] = { + &omap44xx_emif_fw__emif2, +}; + +static struct omap_hwmod omap44xx_emif2_hwmod = { + .name = "emif2", + .class = &omap44xx_emif_hwmod_class, + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_emif2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_emif2_irqs), + .main_clk = "emif2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, + }, + }, + .slaves = omap44xx_emif2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_emif2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), +}; + + +/* * 'fdif' class * face detection hw accelerator module */ @@ -5509,6 +5611,10 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_dss_rfbi_hwmod, &omap44xx_dss_venc_hwmod, + /* emif class */ + &omap44xx_emif1_hwmod, + &omap44xx_emif2_hwmod, + /* gpio class */ &omap443x_gpio1_hwmod, &omap446x_gpio1_hwmod, |