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| author | Rajendra Nayak <rnayak@ti.com> | 2011-07-08 12:44:17 +0530 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2011-07-10 23:53:51 -0700 |
| commit | ebaff49457bcc1cb74074bfec661efd00b85fc5b (patch) | |
| tree | 8e84b16e8e5d33667a20c5c59292781f08cedf71 /arch/arm/mach-omap2/pm44xx.c | |
| parent | 97bfd36d9f874ba9b5b1621e92dcbe762b07c82e (diff) | |
| download | kernel_samsung_tuna-ebaff49457bcc1cb74074bfec661efd00b85fc5b.zip kernel_samsung_tuna-ebaff49457bcc1cb74074bfec661efd00b85fc5b.tar.gz kernel_samsung_tuna-ebaff49457bcc1cb74074bfec661efd00b85fc5b.tar.bz2 | |
OMAP4: PM: Enable the CHIP RET support
Chip RET includes voltage domains scaling to RET voltage. AUTO RET should be
enabled before attempting low power state and AUTO RET should be disabled
immediately after waking up.
Acked-by: Todd Poynor <toddpoynor@google.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Ambresh K <ambresh@ti.com>
[ported to 3.0 and cleanup]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Avinash.H.M. <avinashhm@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/pm44xx.c')
| -rw-r--r-- | arch/arm/mach-omap2/pm44xx.c | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index cc583bf..4c33628 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -41,6 +41,7 @@ #include "smartreflex.h" #include "dvfs.h" #include "voltage.h" +#include "vc.h" struct power_state { struct powerdomain *pwrdm; @@ -102,10 +103,18 @@ void omap4_enter_sleep(unsigned int cpu, unsigned int power_state) pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); } else { omap_sr_disable_reset_volt(mpu_voltdm); + omap_vc_set_auto_trans(mpu_voltdm, + OMAP_VC_CHANNEL_AUTO_TRANSITION_RETENTION); } } if (core_next_state < PWRDM_POWER_ON) { + /* + * Note: IVA can hit RET outside of cpuidle and hence this is + * not the right optimal place to enable IVA AUTO RET. But since + * enabling AUTO RET requires SR to disabled, its done here for + * now. Needs a relook to see if this can be optimized. + */ if (omap_dvfs_is_scaling(core_voltdm) || omap_dvfs_is_scaling(iva_voltdm)) { core_next_state = PWRDM_POWER_ON; @@ -113,6 +122,10 @@ void omap4_enter_sleep(unsigned int cpu, unsigned int power_state) } else { omap_sr_disable_reset_volt(iva_voltdm); omap_sr_disable_reset_volt(core_voltdm); + omap_vc_set_auto_trans(core_voltdm, + OMAP_VC_CHANNEL_AUTO_TRANSITION_RETENTION); + omap_vc_set_auto_trans(iva_voltdm, + OMAP_VC_CHANNEL_AUTO_TRANSITION_RETENTION); omap_uart_prepare_idle(0); omap_uart_prepare_idle(1); @@ -126,6 +139,11 @@ void omap4_enter_sleep(unsigned int cpu, unsigned int power_state) omap4_enter_lowpower(cpu, power_state); if (core_next_state < PWRDM_POWER_ON) { + /* See note above */ + omap_vc_set_auto_trans(core_voltdm, + OMAP_VC_CHANNEL_AUTO_TRANSITION_DISABLE); + omap_vc_set_auto_trans(iva_voltdm, + OMAP_VC_CHANNEL_AUTO_TRANSITION_DISABLE); omap2_gpio_resume_after_idle(); omap_uart_resume_idle(0); omap_uart_resume_idle(1); @@ -135,8 +153,11 @@ void omap4_enter_sleep(unsigned int cpu, unsigned int power_state) omap_sr_enable(core_voltdm); } - if (mpu_next_state < PWRDM_POWER_INACTIVE) + if (mpu_next_state < PWRDM_POWER_INACTIVE) { + omap_vc_set_auto_trans(mpu_voltdm, + OMAP_VC_CHANNEL_AUTO_TRANSITION_DISABLE); omap_sr_enable(mpu_voltdm); + } return; } @@ -433,18 +454,24 @@ static int __init omap4_pm_init(void) pr_err("%s: Failed to get voltdm for VDD MPU\n", __func__); goto err2; } + omap_vc_set_auto_trans(mpu_voltdm, + OMAP_VC_CHANNEL_AUTO_TRANSITION_DISABLE); iva_voltdm = voltdm_lookup("iva"); if (!iva_voltdm) { pr_err("%s: Failed to get voltdm for VDD IVA\n", __func__); goto err2; } + omap_vc_set_auto_trans(iva_voltdm, + OMAP_VC_CHANNEL_AUTO_TRANSITION_DISABLE); core_voltdm = voltdm_lookup("core"); if (!core_voltdm) { pr_err("%s: Failed to get voltdm for VDD CORE\n", __func__); goto err2; } + omap_vc_set_auto_trans(core_voltdm, + OMAP_VC_CHANNEL_AUTO_TRANSITION_DISABLE); ret = omap4_mpuss_init(); if (ret) { |