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author | Suman Anna <s-anna@ti.com> | 2011-03-25 19:49:52 -0500 |
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committer | Colin Cross <ccross@android.com> | 2011-06-14 09:05:25 -0700 |
commit | 729b8d9d0ec2644382f7da75e124228d5d42fa61 (patch) | |
tree | 371ab1f2c418d779fb72ff433bb626892536bcb4 /arch/arm/mach-omap2 | |
parent | 12256aea599a56e2835c3f8230eeae7c22a633f7 (diff) | |
download | kernel_samsung_tuna-729b8d9d0ec2644382f7da75e124228d5d42fa61.zip kernel_samsung_tuna-729b8d9d0ec2644382f7da75e124228d5d42fa61.tar.gz kernel_samsung_tuna-729b8d9d0ec2644382f7da75e124228d5d42fa61.tar.bz2 |
omap4: hwmod: set init_no_reset flag for ipu iommu
This patch fixes a problem with the Ducati boot sequence caused
by an improper AMMU/Unicache state upon a retention->active
transition of CORE domain. The AMMU/Unicache is enabled by the
SCACHE_CONFIG.BYPASS bit - a value of 1 enables the cache and
mandates all addresses accessed by M3 be defined in the AMMU.
This bit is not programmable from the A9-side. The M3 boot
sequence starts out with the AMMU/Unicache in disabled state,
and SYS/BIOS programs the AMMU regions and enables the Unicache
during one of its initial boot steps. Out of retention, the
SCACHE_CONFIG.BYPASS bit is enabled by default, irrespective of
whether it was previously enabled or not.
By not setting this flag in the hwmod database, the hwmod
initialization enables the clocks and deasserts RST3. And when
the CORE domain hits either of OSWR or CSWR, the BYPASS bit gets
auto-set, and the M3 boot throws an exception as soon as the M3
core's reset is deasserted since the boot address is typically
not defined in any valid AMMU regions. Setting this flag allows
an IPC driver to take out the resets as required, after doing the
necessary programming. This also keeps the entire sub-system in
RESET if no IPC driver is selected in the kernel.
Signed-off-by: Suman Anna <s-anna@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 290a2ee..f5158fe 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -2436,6 +2436,7 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = { static struct omap_hwmod omap44xx_ipu_hwmod = { .name = "ipu", .class = &omap44xx_ipu_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_ipu_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs), .rst_lines = omap44xx_ipu_resets, |