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| author | Todd Poynor <toddpoynor@google.com> | 2013-03-13 17:35:08 -0700 |
|---|---|---|
| committer | Todd Poynor <toddpoynor@google.com> | 2013-03-13 17:35:08 -0700 |
| commit | 1249d25539343d1a7fe361c8d40be7a5df5b0216 (patch) | |
| tree | 770c9a33604bb00c62f44d780aefab27e4eb9379 /arch/arm/mach-pxa/smemc.c | |
| parent | 4aad13d07babf68c1d0d37ff1e5f797573c4fd2a (diff) | |
| parent | 0b203ab4aacdb6e6dfb8c277aa290f0a02428e6f (diff) | |
| download | kernel_samsung_tuna-1249d25539343d1a7fe361c8d40be7a5df5b0216.zip kernel_samsung_tuna-1249d25539343d1a7fe361c8d40be7a5df5b0216.tar.gz kernel_samsung_tuna-1249d25539343d1a7fe361c8d40be7a5df5b0216.tar.bz2 | |
Merge branch 'android-3.0' into android-omap-3.0
Diffstat (limited to 'arch/arm/mach-pxa/smemc.c')
| -rw-r--r-- | arch/arm/mach-pxa/smemc.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c index 7992305..f38aa89 100644 --- a/arch/arm/mach-pxa/smemc.c +++ b/arch/arm/mach-pxa/smemc.c @@ -40,6 +40,8 @@ static void pxa3xx_smemc_resume(void) __raw_writel(csadrcfg[1], CSADRCFG1); __raw_writel(csadrcfg[2], CSADRCFG2); __raw_writel(csadrcfg[3], CSADRCFG3); + /* CSMSADRCFG wakes up in its default state (0), so we need to set it */ + __raw_writel(0x2, CSMSADRCFG); } static struct syscore_ops smemc_syscore_ops = { @@ -49,8 +51,19 @@ static struct syscore_ops smemc_syscore_ops = { static int __init smemc_init(void) { - if (cpu_is_pxa3xx()) + if (cpu_is_pxa3xx()) { + /* + * The only documentation we have on the + * Chip Select Configuration Register (CSMSADRCFG) is that + * it must be programmed to 0x2. + * Moreover, in the bit definitions, the second bit + * (CSMSADRCFG[1]) is called "SETALWAYS". + * Other bits are reserved in this register. + */ + __raw_writel(0x2, CSMSADRCFG); + register_syscore_ops(&smemc_syscore_ops); + } return 0; } |