diff options
| author | Ben Dooks <ben-linux@fluff.org> | 2008-04-16 00:12:39 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-04-17 17:04:40 +0100 |
| commit | d96a980441a70168a8ead0a0f23c4c63725da5fa (patch) | |
| tree | 098551e6498fa641caaff62e352d21d7d9383c84 /arch/arm/mach-s3c2410 | |
| parent | 1017be88d341c05adc8d790d8092781b7330dafd (diff) | |
| download | kernel_samsung_tuna-d96a980441a70168a8ead0a0f23c4c63725da5fa.zip kernel_samsung_tuna-d96a980441a70168a8ead0a0f23c4c63725da5fa.tar.gz kernel_samsung_tuna-d96a980441a70168a8ead0a0f23c4c63725da5fa.tar.bz2 | |
[ARM] 4986/1: S3C24XX: Simtec machines need UCLK as parent to DCLK
All current Simtec designs source the DCLK outputs from
the UPLL. This means the DCLK's parent must be set to UPLL
so that anything enabling and disabling an UPLL sourced
clock does not shutdown the DCLK due to missing open counts.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410')
| -rw-r--r-- | arch/arm/mach-s3c2410/mach-bast.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-s3c2410/mach-vr1000.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index b45fb65..518727d 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -592,10 +592,10 @@ static void __init bast_map_io(void) { /* initialise the clocks */ - s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.parent = &clk_upll; s3c24xx_dclk0.rate = 12*1000*1000; - s3c24xx_dclk1.parent = NULL; + s3c24xx_dclk1.parent = &clk_upll; s3c24xx_dclk1.rate = 24*1000*1000; s3c24xx_clkout0.parent = &s3c24xx_dclk0; diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 3aade7b..c564233 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c @@ -393,7 +393,7 @@ static void __init vr1000_map_io(void) { /* initialise clock sources */ - s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.parent = &clk_upll; s3c24xx_dclk0.rate = 12*1000*1000; s3c24xx_dclk1.parent = NULL; |