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| author | David S. Miller <davem@davemloft.net> | 2009-11-18 22:19:03 -0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-11-18 22:19:03 -0800 |
| commit | 3505d1a9fd65e2d3e00827857b6795d9d8983658 (patch) | |
| tree | 941cfafdb57c427bb6b7ebf6354ee93b2a3693b5 /arch/arm/mm/cache-v6.S | |
| parent | dfef948ed2ba69cf041840b5e860d6b4e16fa0b1 (diff) | |
| parent | 66b00a7c93ec782d118d2c03bd599cfd041e80a1 (diff) | |
| download | kernel_samsung_tuna-3505d1a9fd65e2d3e00827857b6795d9d8983658.zip kernel_samsung_tuna-3505d1a9fd65e2d3e00827857b6795d9d8983658.tar.gz kernel_samsung_tuna-3505d1a9fd65e2d3e00827857b6795d9d8983658.tar.bz2 | |
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts:
drivers/net/sfc/sfe4001.c
drivers/net/wireless/libertas/cmd.c
drivers/staging/Kconfig
drivers/staging/Makefile
drivers/staging/rtl8187se/Kconfig
drivers/staging/rtl8192e/Kconfig
Diffstat (limited to 'arch/arm/mm/cache-v6.S')
| -rw-r--r-- | arch/arm/mm/cache-v6.S | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 8f5c13f..295e25d 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -12,6 +12,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/unwind.h> #include "proc-macros.S" @@ -121,11 +122,13 @@ ENTRY(v6_coherent_kern_range) * - the Icache does not read data from the write buffer */ ENTRY(v6_coherent_user_range) - + UNWIND(.fnstart ) #ifdef HARVARD_CACHE bic r0, r0, #CACHE_LINE_SIZE - 1 -1: mcr p15, 0, r0, c7, c10, 1 @ clean D line +1: + USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line add r0, r0, #CACHE_LINE_SIZE +2: cmp r0, r1 blo 1b #endif @@ -143,6 +146,19 @@ ENTRY(v6_coherent_user_range) mov pc, lr /* + * Fault handling for the cache operation above. If the virtual address in r0 + * isn't mapped, just try the next page. + */ +9001: + mov r0, r0, lsr #12 + mov r0, r0, lsl #12 + add r0, r0, #4096 + b 2b + UNWIND(.fnend ) +ENDPROC(v6_coherent_user_range) +ENDPROC(v6_coherent_kern_range) + +/* * v6_flush_kern_dcache_page(kaddr) * * Ensure that the data held in the page kaddr is written back |