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| author | Will Deacon <will.deacon@arm.com> | 2010-09-28 14:02:02 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-10-04 19:20:14 +0100 |
| commit | 475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2d (patch) | |
| tree | c2c3e98575957a0eab1492da35921c982c5d2e1e /arch/arm/mm | |
| parent | c6ea21e35bf3691cad59647c771e6606067f627d (diff) | |
| download | kernel_samsung_tuna-475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2d.zip kernel_samsung_tuna-475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2d.tar.gz kernel_samsung_tuna-475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2d.tar.bz2 | |
ARM: 6416/1: errata: faulty hazard checking in the Store Buffer may lead to data corruption
On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption
can occur under very rare conditions due to a store buffer optimisation.
This workaround sets a bit in the diagnostic register of the Cortex-A9,
disabling the optimisation and preventing the problem from occurring.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 7563ff0..75619c5 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -253,6 +253,14 @@ __v7_setup: orreq r10, r10, #1 << 22 @ set bit #22 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_743622 + teq r6, #0x20 @ present in r2p0 + teqne r6, #0x21 @ present in r2p1 + teqne r6, #0x22 @ present in r2p2 + mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register + orreq r10, r10, #1 << 6 @ set bit #6 + mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif 3: mov r10, #0 #ifdef HARVARD_CACHE |