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author | Ben Dooks <ben-linux@fluff.org> | 2008-11-21 10:36:06 +0000 |
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committer | Ben Dooks <ben-linux@fluff.org> | 2008-12-15 21:46:25 +0000 |
commit | 7d2dbcf9faad074c52a941d01fc21eea3c95ca33 (patch) | |
tree | e06a1dc63a99afd6471d17d228a66226aa321f4d /arch/arm/plat-s3c/pwm-clock.c | |
parent | 82fd8e681d60a195ce6e9fc783d0ebe7a81b1ead (diff) | |
download | kernel_samsung_tuna-7d2dbcf9faad074c52a941d01fc21eea3c95ca33.zip kernel_samsung_tuna-7d2dbcf9faad074c52a941d01fc21eea3c95ca33.tar.gz kernel_samsung_tuna-7d2dbcf9faad074c52a941d01fc21eea3c95ca33.tar.bz2 |
[ARM] S3C: Fix scaler1 clock rate information
The pwm-scaler0 and pwm-scaler1 clocks have their
.id field set to -1 as they are not referenced to
any specific device. However, parts of the pwm-clock
code used the .id field to identify which scaler
clock was being used.
Fix the problem by comparing against the pointer to
the clock to identify the scalers.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c/pwm-clock.c')
-rw-r--r-- | arch/arm/plat-s3c/pwm-clock.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/plat-s3c/pwm-clock.c b/arch/arm/plat-s3c/pwm-clock.c index b0fcbc1..e07d828 100644 --- a/arch/arm/plat-s3c/pwm-clock.c +++ b/arch/arm/plat-s3c/pwm-clock.c @@ -73,11 +73,13 @@ * tclk -------------------------/ */ +static struct clk clk_timer_scaler[]; + static unsigned long clk_pwm_scaler_get_rate(struct clk *clk) { unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0); - if (clk->id == 1) { + if (clk == &clk_timer_scaler[1]) { tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK; tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT; } else { @@ -114,7 +116,7 @@ static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate) local_irq_save(flags); tcfg0 = __raw_readl(S3C2410_TCFG0); - if (clk->id == 1) { + if (clk == &clk_timer_scaler[1]) { tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT; } else { |