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authorRuchika Kharwar <ruchika@ti.com>2012-05-16 19:29:44 +0300
committerZiyann <jaraidaniel@gmail.com>2014-10-01 12:59:21 +0200
commit7575c3316ca64958a2015144756f890944f432ed (patch)
treed99c3aa89c16ec74ad5412af5c2c8955b3669540 /arch/arm
parent03329a82846db43777779dd53e77962741cb0eca (diff)
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OMAP4: DPLL cascading: Recalibrate Baud Rates for UARTs when the DPLL freq changes
This patch attached the callbacks to DPLL framework to recalib. the baud rates of all the UART's base on the functional clock chnages in the DPLL cascading Low Power mode. [Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>: Ported and adapted to p-android-omap-3.0] Change-Id: If60b3287934f8d780b72b3aa68cbeccd52f99658 Signed-off-by: Ruchika Kharwar <ruchika@ti.com> Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-omap/include/plat/omap-serial.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 6386f81..9a5d550 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -146,6 +146,11 @@ struct uart_omap_port {
unsigned char wer;
unsigned char scr;
+#ifdef CONFIG_OMAP4_DPLL_CASCADING
+ unsigned int baud_rate;
+ struct notifier_block nb;
+#endif
+
int use_dma;
bool suspended;
/*