diff options
author | Michael Hennerich <michael.hennerich@analog.com> | 2008-08-06 17:55:32 +0800 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-08-06 17:55:32 +0800 |
commit | 56f5f59052bb662a77d5ffd6cbe5861a2ef2407c (patch) | |
tree | 4c645e253579fa7d3e912144bd317a0236f27a5a /arch/blackfin | |
parent | 15b07536892284449ac5cd9488a8da1054b4295b (diff) | |
download | kernel_samsung_tuna-56f5f59052bb662a77d5ffd6cbe5861a2ef2407c.zip kernel_samsung_tuna-56f5f59052bb662a77d5ffd6cbe5861a2ef2407c.tar.gz kernel_samsung_tuna-56f5f59052bb662a77d5ffd6cbe5861a2ef2407c.tar.bz2 |
Blackfin arch: Fix Bug - System with EMAC driver enabled - Core not idling
- Disable all bits in SIC_IWR unless we are going into a real (DPMC)
power saving mode. Any Interrupt can wake the core form it's idle state.
- Remove deep sleep mode as it is not going to be used anywhere:
We support sleep, sleep deeper and hibernate.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r-- | arch/blackfin/mach-bf527/head.S | 7 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/head.S | 7 | ||||
-rw-r--r-- | arch/blackfin/mach-bf537/head.S | 7 | ||||
-rw-r--r-- | arch/blackfin/mach-bf548/head.S | 7 | ||||
-rw-r--r-- | arch/blackfin/mach-common/dpmc_modes.S | 56 | ||||
-rw-r--r-- | arch/blackfin/mach-common/ints-priority.c | 8 | ||||
-rw-r--r-- | arch/blackfin/mach-common/pm.c | 8 |
7 files changed, 8 insertions, 92 deletions
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S index af20183..2cc46f8 100644 --- a/arch/blackfin/mach-bf527/head.S +++ b/arch/blackfin/mach-bf527/head.S @@ -183,13 +183,6 @@ ENTRY(_start_dma_code) [P2] = R1; SSYNC; - p0.h = hi(SIC_IWR0); - p0.l = lo(SIC_IWR0); - r0.l = lo(IWR_ENABLE_ALL); - r0.h = hi(IWR_ENABLE_ALL); - [p0] = r0; - SSYNC; - RTS; ENDPROC(_start_dma_code) #endif /* CONFIG_BFIN_KERNEL_CLOCK */ diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S index 6603967..184296b 100644 --- a/arch/blackfin/mach-bf533/head.S +++ b/arch/blackfin/mach-bf533/head.S @@ -177,13 +177,6 @@ ENTRY(_start_dma_code) [P2] = R1; SSYNC; - p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); - r0.l = lo(IWR_ENABLE_ALL); - r0.h = hi(IWR_ENABLE_ALL); - [p0] = r0; - SSYNC; - RTS; ENDPROC(_start_dma_code) #endif /* CONFIG_BFIN_KERNEL_CLOCK */ diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index 6a02e47..c02c8ce 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S @@ -197,13 +197,6 @@ ENTRY(_start_dma_code) [P2] = R1; SSYNC; - p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); - r0.l = lo(IWR_ENABLE_ALL); - r0.h = hi(IWR_ENABLE_ALL); - [p0] = r0; - SSYNC; - RTS; ENDPROC(_start_dma_code) #endif /* CONFIG_BFIN_KERNEL_CLOCK */ diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S index cf94e1e..0b18196 100644 --- a/arch/blackfin/mach-bf548/head.S +++ b/arch/blackfin/mach-bf548/head.S @@ -201,13 +201,6 @@ ENTRY(_start_dma_code) SSYNC; #endif - p0.h = hi(SIC_IWR0); - p0.l = lo(SIC_IWR0); - r0.l = lo(IWR_ENABLE_ALL); - r0.h = hi(IWR_ENABLE_ALL); - [p0] = r0; - SSYNC; - RTS; ENDPROC(_start_dma_code) #endif /* CONFIG_BFIN_KERNEL_CLOCK */ diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S index 5e3f1d8..838b0b2 100644 --- a/arch/blackfin/mach-common/dpmc_modes.S +++ b/arch/blackfin/mach-common/dpmc_modes.S @@ -78,62 +78,6 @@ ENTRY(_hibernate_mode) jump .Lforever; ENDPROC(_hibernate_mode) -ENTRY(_deep_sleep) - [--SP] = ( R7:0, P5:0 ); - [--SP] = RETS; - - CLI R4; - - R0 = IWR_ENABLE(0); - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - - call _set_sic_iwr; - - call _set_dram_srfs; - - /* Clear all the interrupts,bits sticky */ - R0 = 0xFFFF (Z); - call _set_rtc_istat - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R0 = W[P0](z); - BITSET (R0, 5); - W[P0] = R0.L; - - call _test_pll_locked; - - SSYNC; - IDLE; - - call _unset_dram_srfs; - - call _test_pll_locked; - - R0 = IWR_ENABLE(0); - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - - call _set_sic_iwr; - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R0 = w[p0](z); - BITCLR (R0, 3); - BITCLR (R0, 5); - BITCLR (R0, 8); - w[p0] = R0; - IDLE; - call _test_pll_locked; - - STI R4; - - RETS = [SP++]; - ( R7:0, P5:0 ) = [SP++]; - RTS; -ENDPROC(_deep_sleep) - ENTRY(_sleep_deeper) [--SP] = ( R7:0, P5:0 ); [--SP] = RETS; diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index e713b9d..4271ef3 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -1068,13 +1068,13 @@ int __init init_arch_irq(void) IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) - bfin_write_SIC_IWR0(IWR_ENABLE_ALL); - bfin_write_SIC_IWR1(IWR_ENABLE_ALL); + bfin_write_SIC_IWR0(IWR_DISABLE_ALL); + bfin_write_SIC_IWR1(IWR_DISABLE_ALL); # ifdef CONFIG_BF54x - bfin_write_SIC_IWR2(IWR_ENABLE_ALL); + bfin_write_SIC_IWR2(IWR_DISABLE_ALL); # endif #else - bfin_write_SIC_IWR(IWR_ENABLE_ALL); + bfin_write_SIC_IWR(IWR_DISABLE_ALL); #endif return 0; diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index 143134b..a17ace3 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c @@ -83,13 +83,13 @@ void bfin_pm_suspend_standby_enter(void) bfin_pm_standby_restore(); #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) - bfin_write_SIC_IWR0(IWR_ENABLE_ALL); - bfin_write_SIC_IWR1(IWR_ENABLE_ALL); + bfin_write_SIC_IWR0(IWR_DISABLE_ALL); + bfin_write_SIC_IWR1(IWR_DISABLE_ALL); # ifdef CONFIG_BF54x - bfin_write_SIC_IWR2(IWR_ENABLE_ALL); + bfin_write_SIC_IWR2(IWR_DISABLE_ALL); # endif #else - bfin_write_SIC_IWR(IWR_ENABLE_ALL); + bfin_write_SIC_IWR(IWR_DISABLE_ALL); #endif local_irq_restore(flags); |