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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-19 19:07:12 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-19 19:07:12 -0700 |
| commit | 25f42b6af09e34c3f92107b36b5aa6edc2fdba2f (patch) | |
| tree | e0977d906193eadeafebc442775491b844be79d5 /arch/mips/mips-boards/sim/sim_smp.c | |
| parent | 4c84a39c8adba6bf2f829b217e78bfd61478191a (diff) | |
| parent | 1723b4a34af85447684c9696af83929d2c1e8e6b (diff) | |
| download | kernel_samsung_tuna-25f42b6af09e34c3f92107b36b5aa6edc2fdba2f.zip kernel_samsung_tuna-25f42b6af09e34c3f92107b36b5aa6edc2fdba2f.tar.gz kernel_samsung_tuna-25f42b6af09e34c3f92107b36b5aa6edc2fdba2f.tar.bz2 | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (51 commits)
[MIPS] Make timer interrupt frequency configurable from kconfig.
[MIPS] Correct HAL2 Kconfig description
[MIPS] Fix R4K cache macro names
[MIPS] Add Missing R4K Cache Macros to IP27 & IP32
[MIPS] Support for the RM9000-based Basler eXcite smart camera platform.
[MIPS] Support for the R5500-based NEC EMMA2RH Mark-eins board
[MIPS] Support SNI RM200C SNI in big endian mode and R5000 processors.
[MIPS] SN: include asm/sn/types.h for nasid_t.
[MIPS] Random fixes for sb1250
[MIPS] Fix bcm1480 compile
[MIPS] Remove support for NEC DDB5476.
[MIPS] Remove support for NEC DDB5074.
[MIPS] Cleanup memory managment initialization.
[MIPS] SN: Declare bridge_pci_ops.
[MIPS] Remove unused function alloc_pci_controller.
[MIPS] IP27: Extract pci_ops into separate file.
[MIPS] IP27: Use symbolic constants instead of magic numbers.
[MIPS] vr41xx: remove unnecessay items from vr41xx/Kconfig.
[MIPS] IP27: Cleanup N/M mode configuration.
[MIPS] IP27: Throw away old unused hacks.
...
Diffstat (limited to 'arch/mips/mips-boards/sim/sim_smp.c')
| -rw-r--r-- | arch/mips/mips-boards/sim/sim_smp.c | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/arch/mips/mips-boards/sim/sim_smp.c b/arch/mips/mips-boards/sim/sim_smp.c index b7084e7..0040709 100644 --- a/arch/mips/mips-boards/sim/sim_smp.c +++ b/arch/mips/mips-boards/sim/sim_smp.c @@ -51,27 +51,6 @@ void core_send_ipi(int cpu, unsigned int action) } /* - * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map - */ - -void __init prom_build_cpu_map(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - int nextslot; - - /* - * As of November, 2004, MIPSsim only simulates one core - * at a time. However, that core may be a MIPS MT core - * with multiple virtual processors and thread contexts. - */ - - if (read_c0_config3() & (1<<2)) { - nextslot = mipsmt_build_cpu_map(1); - } -#endif /* CONFIG_MIPS_MT_SMTC */ -} - -/* * Platform "CPU" startup hook */ |