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| author | Paul Mundt <lethal@linux-sh.org> | 2009-08-15 03:06:41 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2009-08-15 03:06:41 +0900 |
| commit | 8010fbe7a67c2f993cbb11b9d8b7e98528256dd1 (patch) | |
| tree | 861fc7d33fe08b33818b9401f2ba1b32edd82505 /arch/sh/kernel/cpu | |
| parent | 112e58471de3431fbd03dee514777ad4a66a77b2 (diff) | |
| download | kernel_samsung_tuna-8010fbe7a67c2f993cbb11b9d8b7e98528256dd1.zip kernel_samsung_tuna-8010fbe7a67c2f993cbb11b9d8b7e98528256dd1.tar.gz kernel_samsung_tuna-8010fbe7a67c2f993cbb11b9d8b7e98528256dd1.tar.bz2 | |
sh: TLB fast path optimizations for load/store exceptions.
This only bothers with the TLB entry flush in the case of the initial
page write exception, as it is unecessary in the case of the load/store
exceptions.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu')
| -rw-r--r-- | arch/sh/kernel/cpu/sh3/entry.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S index bbaf2bd..a701fac 100644 --- a/arch/sh/kernel/cpu/sh3/entry.S +++ b/arch/sh/kernel/cpu/sh3/entry.S @@ -124,7 +124,7 @@ ENTRY(tlb_miss_store) .align 2 ENTRY(initial_page_write) bra call_handle_tlbmiss - mov #1, r5 + mov #2, r5 .align 2 ENTRY(tlb_protection_violation_load) |