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| author | GuanXuetao <gxt@mprc.pku.edu.cn> | 2011-03-04 18:07:48 +0800 |
|---|---|---|
| committer | GuanXuetao <gxt@mprc.pku.edu.cn> | 2011-03-17 09:19:21 +0800 |
| commit | 1cf46c42d7688a2e09de87fc9201b0e9a0961866 (patch) | |
| tree | f6bba402319785ed745be62e5b655715626d2761 /arch/unicore32/kernel/pci.c | |
| parent | 4fde87cb13a29c06e0b4c2cba86445492098fbc2 (diff) | |
| download | kernel_samsung_tuna-1cf46c42d7688a2e09de87fc9201b0e9a0961866.zip kernel_samsung_tuna-1cf46c42d7688a2e09de87fc9201b0e9a0961866.tar.gz kernel_samsung_tuna-1cf46c42d7688a2e09de87fc9201b0e9a0961866.tar.bz2 | |
unicore32: modify io_p2v and io_v2p macros, and adjust PKUNITY_mmio_BASEs
1. remove __REG macro
2. add (void __iomem *) to io_p2v macro
3. add (phys_addr_t) to io_v2p macro
4. add PKUNITY_AHB_BASE and PKUNITY_APB_BASE definitions
5. modify all PKUNITY_mmio_BASEs from physical addr to virtual addr
6. adjust prefix macro for all usage of PKUNITY_mmio_BASEs
-- by advice with Arnd Bergmann
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/unicore32/kernel/pci.c')
| -rw-r--r-- | arch/unicore32/kernel/pci.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/unicore32/kernel/pci.c b/arch/unicore32/kernel/pci.c index 65c265e..100eab8 100644 --- a/arch/unicore32/kernel/pci.c +++ b/arch/unicore32/kernel/pci.c @@ -75,27 +75,27 @@ void pci_puv3_preinit(void) { printk(KERN_DEBUG "PCI: PKUnity PCI Controller Initializing ...\n"); /* config PCI bridge base */ - writel(PKUNITY_PCIBRI_BASE, PCICFG_BRIBASE); + writel(io_v2p(PKUNITY_PCIBRI_BASE), PCICFG_BRIBASE); writel(0, PCIBRI_AHBCTL0); - writel(PKUNITY_PCIBRI_BASE | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0); + writel(io_v2p(PKUNITY_PCIBRI_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0); writel(0xFFFF0000, PCIBRI_AHBAMR0); writel(0, PCIBRI_AHBTAR0); writel(PCIBRI_CTLx_AT, PCIBRI_AHBCTL1); - writel(PKUNITY_PCILIO_BASE | PCIBRI_BARx_IO, PCIBRI_AHBBAR1); + writel(io_v2p(PKUNITY_PCILIO_BASE) | PCIBRI_BARx_IO, PCIBRI_AHBBAR1); writel(0xFFFF0000, PCIBRI_AHBAMR1); writel(0x00000000, PCIBRI_AHBTAR1); writel(PCIBRI_CTLx_PREF, PCIBRI_AHBCTL2); - writel(PKUNITY_PCIMEM_BASE | PCIBRI_BARx_MEM, PCIBRI_AHBBAR2); + writel(io_v2p(PKUNITY_PCIMEM_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR2); writel(0xF8000000, PCIBRI_AHBAMR2); writel(0, PCIBRI_AHBTAR2); - writel(PKUNITY_PCIAHB_BASE | PCIBRI_BARx_MEM, PCIBRI_BAR1); + writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_BAR1); writel(PCIBRI_CTLx_AT | PCIBRI_CTLx_PREF, PCIBRI_PCICTL0); - writel(PKUNITY_PCIAHB_BASE | PCIBRI_BARx_MEM, PCIBRI_PCIBAR0); + writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_PCIBAR0); writel(0xF8000000, PCIBRI_PCIAMR0); writel(PKUNITY_SDRAM_BASE, PCIBRI_PCITAR0); |