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authorHans Rosenfeld <hans.rosenfeld@amd.com>2011-01-24 16:05:42 +0100
committerIngo Molnar <mingo@elte.hu>2011-01-26 08:28:23 +0100
commit41b2610c3443e6c4760e61fc10eef73f96f9f6a5 (patch)
treec88ed29b417ef4e034c177428cdec320b8a66659 /arch/x86/include
parentb453de02b786c63b8928ec822401468131db0a9b (diff)
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x86, amd: Extend AMD northbridge caching code to support "Link Control" devices
"Link Control" devices (NB function 4) will be used by L3 cache partitioning on family 0x15. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Cc: <andreas.herrmann3@amd.com> LKML-Reference: <1295881543-572552-4-git-send-email-hans.rosenfeld@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include')
-rw-r--r--arch/x86/include/asm/amd_nb.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 64dc82e..3e70700 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -26,6 +26,7 @@ extern void amd_get_nodes(struct bootnode *nodes);
struct amd_northbridge {
struct pci_dev *misc;
+ struct pci_dev *link;
};
struct amd_northbridge_info {