diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-05-02 16:40:20 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-05-02 16:40:20 -0700 |
| commit | 2142babac999a5ba169348892a8e3ac222bec7a4 (patch) | |
| tree | eb862396a9864b34e2335b7cc0c6114c56f9ec1a /arch | |
| parent | bb402c4fb5bba4edf5b8c72b3db8760e60df4876 (diff) | |
| parent | 0516e4643cd22fc9f535aef02ad1de66c382c93b (diff) | |
| download | kernel_samsung_tuna-2142babac999a5ba169348892a8e3ac222bec7a4.zip kernel_samsung_tuna-2142babac999a5ba169348892a8e3ac222bec7a4.tar.gz kernel_samsung_tuna-2142babac999a5ba169348892a8e3ac222bec7a4.tar.bz2 | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (45 commits)
[ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data
[ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created
[ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch
[ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail
davinci: DM644x: NAND: update partitioning
davinci: update DM644x support in preparation for more SoCs
davinci: DM644x: rename board file
davinci: update pin-multiplexing support
davinci: serial: generalize for more SoCs
davinci: DM355 IRQ Definitions
davinci: DM646x: add interrupt number and priorities
davinci: PSC: Clear bits in MDCTL reg before setting new bits
davinci: gpio bugfixes
davinci: add EDMA driver
davinci: timers: use clk_get_rate()
[ARM] pxa/littleton: add missing da9034 touchscreen support
[ARM] pxa/zylonite: configure GPIO18/19 correctly, used by 2 GPIO expanders
[ARM] pxa/zylonite: fix the issue of unused SDATA_IN_1 pin get AC97 not working
[ARM] pxa: make ads7846 on corgi and spitz to sync on HSYNC
[ARM] pxa: remove unused CPU_FREQ_PXA Kconfig symbol
...
Diffstat (limited to 'arch')
70 files changed, 5637 insertions, 970 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e02b893..9faccc4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -486,8 +486,6 @@ config ARCH_PXA select HAVE_CLK select COMMON_CLKDEV select ARCH_REQUIRE_GPIOLIB - select HAVE_CLK - select COMMON_CLKDEV select GENERIC_TIME select GENERIC_CLOCKEVENTS select TICK_ONESHOT @@ -585,6 +583,8 @@ config ARCH_DAVINCI select ARCH_REQUIRE_GPIOLIB select HAVE_CLK select ZONE_DMA + select HAVE_IDE + select COMMON_CLKDEV help Support for TI's DaVinci platform. @@ -740,6 +740,56 @@ if !MMU source "arch/arm/Kconfig-nommu" endif +config ARM_ERRATA_411920 + bool "ARM errata: Invalidation of the Instruction Cache operation can fail" + depends on CPU_V6 && !SMP + help + Invalidation of the Instruction Cache operation can + fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. + It does not affect the MPCore. This option enables the ARM Ltd. + recommended workaround. + +config ARM_ERRATA_430973 + bool "ARM errata: Stale prediction on replaced interworking branch" + depends on CPU_V7 + help + This option enables the workaround for the 430973 Cortex-A8 + (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb + interworking branch is replaced with another code sequence at the + same virtual address, whether due to self-modifying code or virtual + to physical address re-mapping, Cortex-A8 does not recover from the + stale interworking branch prediction. This results in Cortex-A8 + executing the new code sequence in the incorrect ARM or Thumb state. + The workaround enables the BTB/BTAC operations by setting ACTLR.IBE + and also flushes the branch target cache at every context switch. + Note that setting specific bits in the ACTLR register may not be + available in non-secure mode. + +config ARM_ERRATA_458693 + bool "ARM errata: Processor deadlock when a false hazard is created" + depends on CPU_V7 + help + This option enables the workaround for the 458693 Cortex-A8 (r2p0) + erratum. For very specific sequences of memory operations, it is + possible for a hazard condition intended for a cache line to instead + be incorrectly associated with a different cache line. This false + hazard might then cause a processor deadlock. The workaround enables + the L1 caching of the NEON accesses and disables the PLD instruction + in the ACTLR register. Note that setting specific bits in the ACTLR + register may not be available in non-secure mode. + +config ARM_ERRATA_460075 + bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" + depends on CPU_V7 + help + This option enables the workaround for the 460075 Cortex-A8 (r2p0) + erratum. Any asynchronous access to the L2 cache may encounter a + situation in which recent store transactions to the L2 cache are lost + and overwritten with stale memory contents from external memory. The + workaround disables the write-allocate mode for the L2 cache via the + ACTLR register. Note that setting specific bits in the ACTLR register + may not be available in non-secure mode. + endmenu source "arch/arm/common/Kconfig" @@ -1171,12 +1221,6 @@ config CPU_FREQ_IMX If in doubt, say N. -config CPU_FREQ_PXA - bool - depends on CPU_FREQ && ARCH_PXA && PXA25x - default y - select CPU_FREQ_DEFAULT_GOV_USERSPACE - endif source "drivers/cpuidle/Kconfig" diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig new file mode 100644 index 0000000..eb2738b --- /dev/null +++ b/arch/arm/configs/davinci_all_defconfig @@ -0,0 +1,1784 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-rc2 +# Wed Apr 15 08:16:53 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +CONFIG_ARCH_DAVINCI=y +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set + +# +# TI DaVinci Implementations +# + +# +# DaVinci Core Type +# +CONFIG_ARCH_DAVINCI_DM644x=y + +# +# DaVinci Board Type +# +CONFIG_MACH_DAVINCI_EVM=y +CONFIG_DAVINCI_MUX=y +CONFIG_DAVINCI_MUX_DEBUG=y +CONFIG_DAVINCI_MUX_WARNINGS=y +CONFIG_DAVINCI_RESET_CLOCKS=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=m +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=m +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=m +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=m +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=m +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_NAND_DAVINCI=m +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=32768 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +CONFIG_IDE=m + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +CONFIG_IDE_XFER_MODE=y +CONFIG_IDE_TIMINGS=y +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=m +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y +CONFIG_BLK_DEV_PALMCHIP_BK3710=m +CONFIG_BLK_DEV_IDEDMA=y + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_LXT_PHY=y +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +CONFIG_LSI_ET1011C_PHY=y +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=m +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_XTKBD=m +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_DAVINCI=y +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +CONFIG_GPIO_PCF857X=m + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_DAVINCI_WATCHDOG=m + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_V4L_USB_DRIVERS is not set +# CONFIG_RADIO_ADAPTERS is not set +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=m +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +CONFIG_SND_SOC=m +# CONFIG_SND_DAVINCI_SOC is not set +CONFIG_SND_SOC_I2C_AND_SPI=m +# CONFIG_SND_SOC_ALL_CODECS is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=m +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=m +CONFIG_HID_APPLE=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +# CONFIG_DRAGONRISE_FF is not set +CONFIG_HID_EZKEY=m +# CONFIG_HID_KYE is not set +CONFIG_HID_GYRATION=m +# CONFIG_HID_KENSINGTON is not set +CONFIG_HID_LOGITECH=m +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +# CONFIG_HID_NTRIG is not set +CONFIG_HID_PANTHERLORD=m +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_HID_SUNPLUS=m +# CONFIG_GREENASIA_FF is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=m +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=m +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_SOC=y + +# +# DaVinci 35x and 644x USB support +# +# CONFIG_USB_MUSB_HOST is not set +CONFIG_USB_MUSB_PERIPHERAL=y +# CONFIG_USB_MUSB_OTG is not set +CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_MUSB_PIO_ONLY=y +# CONFIG_USB_MUSB_DEBUG is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG is not set +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_GADGET_DEBUG_FS=y +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=m +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=m +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_BD2802 is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=m + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=m +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=m +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig index 30f463d..6ab5dd5 100644 --- a/arch/arm/configs/viper_defconfig +++ b/arch/arm/configs/viper_defconfig @@ -298,7 +298,6 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=m CONFIG_CPU_FREQ_GOV_USERSPACE=m CONFIG_CPU_FREQ_GOV_ONDEMAND=m CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -CONFIG_CPU_FREQ_PXA=y # # Floating point emulation diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index bac988e..a9c78bc 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -4,19 +4,56 @@ menu "TI DaVinci Implementations" comment "DaVinci Core Type" -config ARCH_DAVINCI644x - default y +config ARCH_DAVINCI_DM644x bool "DaVinci 644x based system" comment "DaVinci Board Type" config MACH_DAVINCI_EVM - bool "TI DaVinci EVM" + bool "TI DM644x EVM" default y - depends on ARCH_DAVINCI644x + depends on ARCH_DAVINCI_DM644x help Configure this option to specify the whether the board used - for development is a DaVinci EVM + for development is a DM644x EVM + + +config DAVINCI_MUX + bool "DAVINCI multiplexing support" + depends on ARCH_DAVINCI + default y + help + Pin multiplexing support for DAVINCI boards. If your bootloader + sets the multiplexing correctly, say N. Otherwise, or if unsure, + say Y. + +config DAVINCI_MUX_DEBUG + bool "Multiplexing debug output" + depends on DAVINCI_MUX + help + Makes the multiplexing functions print out a lot of debug info. + This is useful if you want to find out the correct values of the + multiplexing registers. + +config DAVINCI_MUX_WARNINGS + bool "Warn about pins the bootloader didn't set up" + depends on DAVINCI_MUX + help + Choose Y here to warn whenever driver initialization logic needs + to change the pin multiplexing setup. When there are no warnings + printed, it's safe to deselect DAVINCI_MUX for your product. + +config DAVINCI_RESET_CLOCKS + bool "Reset unused clocks during boot" + depends on ARCH_DAVINCI + help + Say Y if you want to reset unused clocks during boot. + This option saves power, but assumes all drivers are + using the clock framework. Broken drivers that do not + yet use clock framework may not work with this option. + If you are booting from another operating system, you + probably do not want this option enabled until your + device drivers work properly. endmenu diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 4dc4585..1674661 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,7 +5,12 @@ # Common objects obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \ - gpio.o mux.o devices.o usb.o + gpio.o devices.o dma.o usb.o + +obj-$(CONFIG_DAVINCI_MUX) += mux.o + +# Chip specific +obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o # Board specific -obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o +obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 0b97a52..c039674 100644 --- a/arch/arm/mach-davinci/board-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -15,15 +15,20 @@ #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/leds.h> +#include <linux/memory.h> +#include <linux/etherdevice.h> #include <linux/i2c.h> #include <linux/i2c/pcf857x.h> #include <linux/i2c/at24.h> #include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <linux/io.h> +#include <linux/phy.h> +#include <linux/clk.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -32,25 +37,34 @@ #include <asm/mach/map.h> #include <asm/mach/flash.h> -#include <mach/hardware.h> +#include <mach/dm644x.h> #include <mach/common.h> #include <mach/i2c.h> +#include <mach/serial.h> +#include <mach/mux.h> +#include <mach/psc.h> +#include <mach/nand.h> -/* other misc. init functions */ -void __init davinci_psc_init(void); -void __init davinci_irq_init(void); -void __init davinci_map_common_io(void); -void __init davinci_init_common_hw(void); +#define DM644X_EVM_PHY_MASK (0x2) +#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ -#if defined(CONFIG_MTD_PHYSMAP) || \ - defined(CONFIG_MTD_PHYSMAP_MODULE) +#define DAVINCI_CFC_ATA_BASE 0x01C66000 + +#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000 + +#define LXT971_PHY_ID (0x001378e2) +#define LXT971_PHY_MASK (0xfffffff0) static struct mtd_partition davinci_evm_norflash_partitions[] = { - /* bootloader (U-Boot, etc) in first 4 sectors */ + /* bootloader (UBL, U-Boot, etc) in first 5 sectors */ { .name = "bootloader", .offset = 0, - .size = 4 * SZ_64K, + .size = 5 * SZ_64K, .mask_flags = MTD_WRITEABLE, /* force read-only */ }, /* bootloader params in the next 1 sectors */ @@ -100,10 +114,89 @@ static struct platform_device davinci_evm_norflash_device = { .resource = &davinci_evm_norflash_resource, }; -#endif +/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks). + * It may used instead of the (default) NOR chip to boot, using TI's + * tools to install the secondary boot loader (UBL) and U-Boot. + */ +struct mtd_partition davinci_evm_nandflash_partition[] = { + /* Bootloader layout depends on whose u-boot is installed, but we + * can hide all the details. + * - block 0 for u-boot environment ... in mainline u-boot + * - block 1 for UBL (plus up to four backup copies in blocks 2..5) + * - blocks 6...? for u-boot + * - blocks 16..23 for u-boot environment ... in TI's u-boot + */ + { + .name = "bootloader", + .offset = 0, + .size = SZ_256K + SZ_128K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* Kernel */ + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, + /* File system (older GIT kernels started this on the 5MB mark) */ + { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* A few blocks at end hold a flash BBT ... created by TI's CCS + * using flashwriter_nand.out, but ignored by TI's versions of + * Linux and u-boot. We boot faster by using them. + */ +}; -#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ - defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) +static struct davinci_nand_pdata davinci_evm_nandflash_data = { + .parts = davinci_evm_nandflash_partition, + .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT, +}; + +static struct resource davinci_evm_nandflash_resource[] = { + { + .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, + .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, + }, { + .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, + .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device davinci_evm_nandflash_device = { + .name = "davinci_nand", + .id = 0, + .dev = { + .platform_data = &davinci_evm_nandflash_data, + }, + .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource), + .resource = davinci_evm_nandflash_resource, +}; + +static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device davinci_fb_device = { + .name = "davincifb", + .id = -1, + .dev = { + .dma_mask = &davinci_fb_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = 0, +}; + +static struct platform_device rtc_dev = { + .name = "rtc_davinci_evm", + .id = -1, +}; static struct resource ide_resources[] = { { @@ -118,7 +211,7 @@ static struct resource ide_resources[] = { }, }; -static u64 ide_dma_mask = DMA_BIT_MASK(32); +static u64 ide_dma_mask = DMA_32BIT_MASK; static struct platform_device ide_dev = { .name = "palm_bk3710", @@ -127,12 +220,10 @@ static struct platform_device ide_dev = { .num_resources = ARRAY_SIZE(ide_resources), .dev = { .dma_mask = &ide_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), + .coherent_dma_mask = DMA_32BIT_MASK, }, }; -#endif - /*----------------------------------------------------------------------*/ /* @@ -311,7 +402,9 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c) gpio_request(gpio + 7, "nCF_SEL"); gpio_direction_output(gpio + 7, 1); - /* irlml6401 sustains over 3A, switches 5V in under 8 msec */ + /* irlml6401 switches over 1A, in under 8 msec; + * now it can be managed by nDRV_VBUS ... + */ setup_usb(500, 8); return 0; @@ -343,14 +436,120 @@ static struct pcf857x_platform_data pcf_data_u35 = { * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL) * - ... newer boards may have more */ +static struct memory_accessor *at24_mem_acc; + +static void at24_setup(struct memory_accessor *mem_acc, void *context) +{ + DECLARE_MAC_BUF(mac_str); + char mac_addr[6]; + + at24_mem_acc = mem_acc; + + /* Read MAC addr from EEPROM */ + if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x7f00, 6) == 6) { + printk(KERN_INFO "Read MAC addr from EEPROM: %s\n", + print_mac(mac_str, mac_addr)); + } +} + static struct at24_platform_data eeprom_info = { .byte_len = (256*1024) / 8, .page_size = 64, .flags = AT24_FLAG_ADDR16, + .setup = at24_setup, }; +int dm6446evm_eeprom_read(void *buf, off_t off, size_t count) +{ + if (at24_mem_acc) + return at24_mem_acc->read(at24_mem_acc, buf, off, count); + return -ENODEV; +} +EXPORT_SYMBOL(dm6446evm_eeprom_read); + +int dm6446evm_eeprom_write(void *buf, off_t off, size_t count) +{ + if (at24_mem_acc) + return at24_mem_acc->write(at24_mem_acc, buf, off, count); + return -ENODEV; +} +EXPORT_SYMBOL(dm6446evm_eeprom_write); + +/* + * MSP430 supports RTC, card detection, input from IR remote, and + * a bit more. It triggers interrupts on GPIO(7) from pressing + * buttons on the IR remote, and for card detect switches. + */ +static struct i2c_client *dm6446evm_msp; + +static int dm6446evm_msp_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + dm6446evm_msp = client; + return 0; +} + +static int dm6446evm_msp_remove(struct i2c_client *client) +{ + dm6446evm_msp = NULL; + return 0; +} + +static const struct i2c_device_id dm6446evm_msp_ids[] = { + { "dm6446evm_msp", 0, }, + { /* end of list */ }, +}; + +static struct i2c_driver dm6446evm_msp_driver = { + .driver.name = "dm6446evm_msp", + .id_table = dm6446evm_msp_ids, + .probe = dm6446evm_msp_probe, + .remove = dm6446evm_msp_remove, +}; + +static int dm6444evm_msp430_get_pins(void) +{ + static const char txbuf[2] = { 2, 4, }; + char buf[4]; + struct i2c_msg msg[2] = { + { + .addr = dm6446evm_msp->addr, + .flags = 0, + .len = 2, + .buf = (void __force *)txbuf, + }, + { + .addr = dm6446evm_msp->addr, + .flags = I2C_M_RD, + .len = 4, + .buf = buf, + }, + }; + int status; + + if (!dm6446evm_msp) + return -ENXIO; + + /* Command 4 == get input state, returns port 2 and port3 data + * S Addr W [A] len=2 [A] cmd=4 [A] + * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P + */ + status = i2c_transfer(dm6446evm_msp->adapter, msg, 2); + if (status < 0) + return status; + + dev_dbg(&dm6446evm_msp->dev, + "PINS: %02x %02x %02x %02x\n", + buf[0], buf[1], buf[2], buf[3]); + + return (buf[3] << 8) | buf[2]; +} + static struct i2c_board_info __initdata i2c_info[] = { { + I2C_BOARD_INFO("dm6446evm_msp", 0x23), + }, + { I2C_BOARD_INFO("pcf8574", 0x38), .platform_data = &pcf_data_u2, }, @@ -368,7 +567,6 @@ static struct i2c_board_info __initdata i2c_info[] = { }, /* ALSO: * - tvl320aic33 audio codec (0x1b) - * - msp430 microcontroller (0x23) * - tvp5146 video decoder (0x5d) */ }; @@ -384,51 +582,109 @@ static struct davinci_i2c_platform_data i2c_pdata = { static void __init evm_init_i2c(void) { davinci_init_i2c(&i2c_pdata); + i2c_add_driver(&dm6446evm_msp_driver); i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); } static struct platform_device *davinci_evm_devices[] __initdata = { -#if defined(CONFIG_MTD_PHYSMAP) || \ - defined(CONFIG_MTD_PHYSMAP_MODULE) - &davinci_evm_norflash_device, -#endif -#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ - defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) - &ide_dev, -#endif + &davinci_fb_device, + &rtc_dev, +}; + +static struct davinci_uart_config uart_config __initdata = { + .enabled_uarts = (1 << 0), }; static void __init davinci_evm_map_io(void) { davinci_map_common_io(); + dm644x_init(); } -static __init void davinci_evm_init(void) +static int davinci_phy_fixup(struct phy_device *phydev) { - davinci_psc_init(); + unsigned int control; + /* CRITICAL: Fix for increasing PHY signal drive strength for + * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY + * signal strength was low causing TX to fail randomly. The + * fix is to Set bit 11 (Increased MII drive strength) of PHY + * register 26 (Digital Config register) on this phy. */ + control = phy_read(phydev, 26); + phy_write(phydev, 26, (control | 0x800)); + return 0; +} #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) +#define HAS_ATA 1 +#else +#define HAS_ATA 0 +#endif + #if defined(CONFIG_MTD_PHYSMAP) || \ defined(CONFIG_MTD_PHYSMAP_MODULE) - printk(KERN_WARNING "WARNING: both IDE and NOR flash are enabled, " - "but share pins.\n\t Disable IDE for NOR support.\n"); +#define HAS_NOR 1 +#else +#define HAS_NOR 0 #endif + +#if defined(CONFIG_MTD_NAND_DAVINCI) || \ + defined(CONFIG_MTD_NAND_DAVINCI_MODULE) +#define HAS_NAND 1 +#else +#define HAS_NAND 0 #endif +static __init void davinci_evm_init(void) +{ + struct clk *aemif_clk; + + aemif_clk = clk_get(NULL, "aemif"); + clk_enable(aemif_clk); + + if (HAS_ATA) { + if (HAS_NAND || HAS_NOR) + pr_warning("WARNING: both IDE and Flash are " + "enabled, but they share AEMIF pins.\n" + "\tDisable IDE for NAND/NOR support.\n"); + davinci_cfg_reg(DM644X_HPIEN_DISABLE); + davinci_cfg_reg(DM644X_ATAEN); + davinci_cfg_reg(DM644X_HDIREN); + platform_device_register(&ide_dev); + } else if (HAS_NAND || HAS_NOR) { + davinci_cfg_reg(DM644X_HPIEN_DISABLE); + davinci_cfg_reg(DM644X_ATAEN_DISABLE); + + /* only one device will be jumpered and detected */ + if (HAS_NAND) { + platform_device_register(&davinci_evm_nandflash_device); + evm_leds[7].default_trigger = "nand-disk"; + if (HAS_NOR) + pr_warning("WARNING: both NAND and NOR flash " + "are enabled; disable one of them.\n"); + } else if (HAS_NOR) + platform_device_register(&davinci_evm_norflash_device); + } + platform_add_devices(davinci_evm_devices, ARRAY_SIZE(davinci_evm_devices)); evm_init_i2c(); + + davinci_serial_init(&uart_config); + + /* Register the fixup for PHY on DaVinci */ + phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, + davinci_phy_fixup); + } static __init void davinci_evm_irq_init(void) { - davinci_init_common_hw(); davinci_irq_init(); } -MACHINE_START(DAVINCI_EVM, "DaVinci EVM") +MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") /* Maintainer: MontaVista Software <source@mvista.com> */ .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index abb92b7..f0baaa1 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -1,7 +1,8 @@ /* - * TI DaVinci clock config file + * Clock and PLL control for DaVinci devices * - * Copyright (C) 2006 Texas Instruments. + * Copyright (C) 2006-2007 Texas Instruments. + * Copyright (C) 2008-2009 Deep Root Systems, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,6 +14,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/errno.h> +#include <linux/clk.h> #include <linux/err.h> #include <linux/mutex.h> #include <linux/platform_device.h> @@ -21,98 +23,50 @@ #include <mach/hardware.h> #include <mach/psc.h> +#include <mach/cputype.h> #include "clock.h" -/* PLL/Reset register offsets */ -#define PLLM 0x110 - static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clockfw_lock); -static unsigned int commonrate; -static unsigned int armrate; -static unsigned int fixedrate = 27000000; /* 27 MHZ */ - -extern void davinci_psc_config(unsigned int domain, unsigned int id, char enable); - -/* - * Returns a clock. Note that we first try to use device id on the bus - * and clock name. If this fails, we try to use clock name only. - */ -struct clk *clk_get(struct device *dev, const char *id) +static unsigned psc_domain(struct clk *clk) { - struct clk *p, *clk = ERR_PTR(-ENOENT); - int idno; - - if (dev == NULL || dev->bus != &platform_bus_type) - idno = -1; - else - idno = to_platform_device(dev)->id; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(p, &clocks, node) { - if (p->id == idno && - strcmp(id, p->name) == 0 && try_module_get(p->owner)) { - clk = p; - goto found; - } - } - - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { - clk = p; - break; - } - } - -found: - mutex_unlock(&clocks_mutex); - - return clk; + return (clk->flags & PSC_DSP) + ? DAVINCI_GPSC_DSPDOMAIN + : DAVINCI_GPSC_ARMDOMAIN; } -EXPORT_SYMBOL(clk_get); -void clk_put(struct clk *clk) +static void __clk_enable(struct clk *clk) { - if (clk && !IS_ERR(clk)) - module_put(clk->owner); -} -EXPORT_SYMBOL(clk_put); - -static int __clk_enable(struct clk *clk) -{ - if (clk->flags & ALWAYS_ENABLED) - return 0; - - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1); - return 0; + if (clk->parent) + __clk_enable(clk->parent); + if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) + davinci_psc_config(psc_domain(clk), clk->lpsc, 1); } static void __clk_disable(struct clk *clk) { - if (clk->usecount) + if (WARN_ON(clk->usecount == 0)) return; - - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0); + if (--clk->usecount == 0 && !(clk->flags & CLK_PLL)) + davinci_psc_config(psc_domain(clk), clk->lpsc, 0); + if (clk->parent) + __clk_disable(clk->parent); } int clk_enable(struct clk *clk) { unsigned long flags; - int ret = 0; if (clk == NULL || IS_ERR(clk)) return -EINVAL; - if (clk->usecount++ == 0) { - spin_lock_irqsave(&clockfw_lock, flags); - ret = __clk_enable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - } + spin_lock_irqsave(&clockfw_lock, flags); + __clk_enable(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); - return ret; + return 0; } EXPORT_SYMBOL(clk_enable); @@ -123,11 +77,9 @@ void clk_disable(struct clk *clk) if (clk == NULL || IS_ERR(clk)) return; - if (clk->usecount > 0 && !(--clk->usecount)) { - spin_lock_irqsave(&clockfw_lock, flags); - __clk_disable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - } + spin_lock_irqsave(&clockfw_lock, flags); + __clk_disable(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); } EXPORT_SYMBOL(clk_disable); @@ -136,7 +88,7 @@ unsigned long clk_get_rate(struct clk *clk) if (clk == NULL || IS_ERR(clk)) return -EINVAL; - return *(clk->rate); + return clk->rate; } EXPORT_SYMBOL(clk_get_rate); @@ -145,7 +97,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) if (clk == NULL || IS_ERR(clk)) return -EINVAL; - return *(clk->rate); + return clk->rate; } EXPORT_SYMBOL(clk_round_rate); @@ -164,10 +116,23 @@ int clk_register(struct clk *clk) if (clk == NULL || IS_ERR(clk)) return -EINVAL; + if (WARN(clk->parent && !clk->parent->rate, + "CLK: %s parent %s has no rate!\n", + clk->name, clk->parent->name)) + return -EINVAL; + mutex_lock(&clocks_mutex); - list_add(&clk->node, &clocks); + list_add_tail(&clk->node, &clocks); mutex_unlock(&clocks_mutex); + /* If rate is already set, use it */ + if (clk->rate) + return 0; + + /* Otherwise, default to parent rate */ + if (clk->parent) + clk->rate = clk->parent->rate; + return 0; } EXPORT_SYMBOL(clk_register); @@ -183,84 +148,150 @@ void clk_unregister(struct clk *clk) } EXPORT_SYMBOL(clk_unregister); -static struct clk davinci_clks[] = { - { - .name = "ARMCLK", - .rate = &armrate, - .lpsc = -1, - .flags = ALWAYS_ENABLED, - }, - { - .name = "UART", - .rate = &fixedrate, - .lpsc = DAVINCI_LPSC_UART0, - }, - { - .name = "EMACCLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, - }, - { - .name = "I2CCLK", - .rate = &fixedrate, - .lpsc = DAVINCI_LPSC_I2C, - }, - { - .name = "IDECLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_ATA, - }, - { - .name = "McBSPCLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_McBSP, - }, - { - .name = "MMCSDCLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_MMC_SD, - }, - { - .name = "SPICLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_SPI, - }, - { - .name = "gpio", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_GPIO, - }, - { - .name = "usb", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_USB, - }, - { - .name = "AEMIFCLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_AEMIF, - .usecount = 1, +#ifdef CONFIG_DAVINCI_RESET_CLOCKS +/* + * Disable any unused clocks left on by the bootloader + */ +static int __init clk_disable_unused(void) +{ + struct clk *ck; + + spin_lock_irq(&clockfw_lock); + list_for_each_entry(ck, &clocks, node) { + if (ck->usecount > 0) + continue; + if (!(ck->flags & CLK_PSC)) + continue; + + /* ignore if in Disabled or SwRstDisable states */ + if (!davinci_psc_is_clk_active(ck->lpsc)) + continue; + + pr_info("Clocks: disable unused %s\n", ck->name); + davinci_psc_config(psc_domain(ck), ck->lpsc, 0); } -}; + spin_unlock_irq(&clockfw_lock); + + return 0; +} +late_initcall(clk_disable_unused); +#endif -int __init davinci_clk_init(void) +static void clk_sysclk_recalc(struct clk *clk) { - struct clk *clkp; - int count = 0; - u32 pll_mult; - - pll_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); - commonrate = ((pll_mult + 1) * 27000000) / 6; - armrate = ((pll_mult + 1) * 27000000) / 2; - - for (clkp = davinci_clks; count < ARRAY_SIZE(davinci_clks); - count++, clkp++) { - clk_register(clkp); - - /* Turn on clocks that have been enabled in the - * table above */ - if (clkp->usecount) - clk_enable(clkp); + u32 v, plldiv; + struct pll_data *pll; + + /* If this is the PLL base clock, no more calculations needed */ + if (clk->pll_data) + return; + + if (WARN_ON(!clk->parent)) + return; + + clk->rate = clk->parent->rate; + + /* Otherwise, the parent must be a PLL */ + if (WARN_ON(!clk->parent->pll_data)) + return; + + pll = clk->parent->pll_data; + + /* If pre-PLL, source clock is before the multiplier and divider(s) */ + if (clk->flags & PRE_PLL) + clk->rate = pll->input_rate; + + if (!clk->div_reg) + return; + + v = __raw_readl(pll->base + clk->div_reg); + if (v & PLLDIV_EN) { + plldiv = (v & PLLDIV_RATIO_MASK) + 1; + if (plldiv) + clk->rate /= plldiv; + } +} + +static void __init clk_pll_init(struct clk *clk) +{ + u32 ctrl, mult = 1, prediv = 1, postdiv = 1; + u8 bypass; + struct pll_data *pll = clk->pll_data; + + pll->base = IO_ADDRESS(pll->phys_base); + ctrl = __raw_readl(pll->base + PLLCTL); + clk->rate = pll->input_rate = clk->parent->rate; + + if (ctrl & PLLCTL_PLLEN) { + bypass = 0; + mult = __raw_readl(pll->base + PLLM); + mult = (mult & PLLM_PLLM_MASK) + 1; + } else + bypass = 1; + + if (pll->flags & PLL_HAS_PREDIV) { + prediv = __raw_readl(pll->base + PREDIV); + if (prediv & PLLDIV_EN) + prediv = (prediv & PLLDIV_RATIO_MASK) + 1; + else + prediv = 1; + } + + /* pre-divider is fixed, but (some?) chips won't report that */ + if (cpu_is_davinci_dm355() && pll->num == 1) + prediv = 8; + + if (pll->flags & PLL_HAS_POSTDIV) { + postdiv = __raw_readl(pll->base + POSTDIV); + if (postdiv & PLLDIV_EN) + postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; + else + postdiv = 1; + } + + if (!bypass) { + clk->rate /= prediv; + clk->rate *= mult; + clk->rate /= postdiv; + } + + pr_debug("PLL%d: input = %lu MHz [ ", + pll->num, clk->parent->rate / 1000000); + if (bypass) + pr_debug("bypass "); + if (prediv > 1) + pr_debug("/ %d ", prediv); + if (mult > 1) + pr_debug("* %d ", mult); + if (postdiv > 1) + pr_debug("/ %d ", postdiv); + pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000); +} + +int __init davinci_clk_init(struct davinci_clk *clocks) + { + struct davinci_clk *c; + struct clk *clk; + + for (c = clocks; c->lk.clk; c++) { + clk = c->lk.clk; + + if (clk->pll_data) + clk_pll_init(clk); + + /* Calculate rates for PLL-derived clocks */ + else if (clk->flags & CLK_PLL) + clk_sysclk_recalc(clk); + + if (clk->lpsc) + clk->flags |= CLK_PSC; + + clkdev_add(&c->lk); + clk_register(clk); + + /* Turn on clocks that Linux doesn't otherwise manage */ + if (clk->flags & ALWAYS_ENABLED) + clk_enable(clk); } return 0; @@ -285,12 +316,52 @@ static void davinci_ck_stop(struct seq_file *m, void *v) { } -static int davinci_ck_show(struct seq_file *m, void *v) +#define CLKNAME_MAX 10 /* longest clock name */ +#define NEST_DELTA 2 +#define NEST_MAX 4 + +static void +dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) { - struct clk *cp; + char *state; + char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX]; + struct clk *clk; + unsigned i; + + if (parent->flags & CLK_PLL) + state = "pll"; + else if (parent->flags & CLK_PSC) + state = "psc"; + else + state = ""; + + /* <nest spaces> name <pad to end> */ + memset(buf, ' ', sizeof(buf) - 1); + buf[sizeof(buf) - 1] = 0; + i = strlen(parent->name); + memcpy(buf + nest, parent->name, + min(i, (unsigned)(sizeof(buf) - 1 - nest))); + + seq_printf(s, "%s users=%2d %-3s %9ld Hz\n", + buf, parent->usecount, state, clk_get_rate(parent)); + /* REVISIT show device associations too */ + + /* cost is now small, but not linear... */ + list_for_each_entry(clk, &clocks, node) { + if (clk->parent == parent) + dump_clock(s, nest + NEST_DELTA, clk); + } +} - list_for_each_entry(cp, &clocks, node) - seq_printf(m,"%s %d %d\n", cp->name, *(cp->rate), cp->usecount); +static int davinci_ck_show(struct seq_file *m, void *v) +{ + /* Show clock tree; we know the main oscillator is first. + * We trust nonzero usecounts equate to PSC enables... + */ + mutex_lock(&clocks_mutex); + if (!list_empty(&clocks)) + dump_clock(m, 0, list_first_entry(&clocks, struct clk, node)); + mutex_unlock(&clocks_mutex); return 0; } @@ -321,4 +392,4 @@ static int __init davinci_ck_proc_init(void) } __initcall(davinci_ck_proc_init); -#endif /* CONFIG_DEBUG_PROC_FS */ +#endif /* CONFIG_DEBUG_PROC_FS */ diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index ed47079..35736ec 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -1,7 +1,8 @@ /* * TI DaVinci clock definitions * - * Copyright (C) 2006 Texas Instruments. + * Copyright (C) 2006-2007 Texas Instruments. + * Copyright (C) 2008-2009 Deep Root Systems, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -11,23 +12,85 @@ #ifndef __ARCH_ARM_DAVINCI_CLOCK_H #define __ARCH_ARM_DAVINCI_CLOCK_H +#include <linux/list.h> +#include <asm/clkdev.h> + +#define DAVINCI_PLL1_BASE 0x01c40800 +#define DAVINCI_PLL2_BASE 0x01c40c00 +#define MAX_PLL 2 + +/* PLL/Reset register offsets */ +#define PLLCTL 0x100 +#define PLLCTL_PLLEN BIT(0) +#define PLLCTL_CLKMODE BIT(8) + +#define PLLM 0x110 +#define PLLM_PLLM_MASK 0xff + +#define PREDIV 0x114 +#define PLLDIV1 0x118 +#define PLLDIV2 0x11c +#define PLLDIV3 0x120 +#define POSTDIV 0x128 +#define BPDIV 0x12c +#define PLLCMD 0x138 +#define PLLSTAT 0x13c +#define PLLALNCTL 0x140 +#define PLLDCHANGE 0x144 +#define PLLCKEN 0x148 +#define PLLCKSTAT 0x14c +#define PLLSYSTAT 0x150 +#define PLLDIV4 0x160 +#define PLLDIV5 0x164 +#define PLLDIV6 0x168 +#define PLLDIV7 0x16c +#define PLLDIV8 0x170 +#define PLLDIV9 0x174 +#define PLLDIV_EN BIT(15) +#define PLLDIV_RATIO_MASK 0x1f + +struct pll_data { + u32 phys_base; + void __iomem *base; + u32 num; + u32 flags; + u32 input_rate; +}; +#define PLL_HAS_PREDIV 0x01 +#define PLL_HAS_POSTDIV 0x02 + struct clk { struct list_head node; struct module *owner; const char *name; - unsigned int *rate; - int id; - __s8 usecount; - __u8 flags; - __u8 lpsc; + unsigned long rate; + u8 usecount; + u8 flags; + u8 lpsc; + struct clk *parent; + struct pll_data *pll_data; + u32 div_reg; }; /* Clock flags */ -#define RATE_CKCTL 1 -#define RATE_FIXED 2 -#define RATE_PROPAGATES 4 -#define VIRTUAL_CLOCK 8 -#define ALWAYS_ENABLED 16 -#define ENABLE_REG_32BIT 32 +#define ALWAYS_ENABLED BIT(1) +#define CLK_PSC BIT(2) +#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ +#define CLK_PLL BIT(4) /* PLL-derived clock */ +#define PRE_PLL BIT(5) /* source is before PLL mult/div */ + +struct davinci_clk { + struct clk_lookup lk; +}; + +#define CLK(dev, con, ck) \ + { \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + }, \ + } +int davinci_clk_init(struct davinci_clk *clocks); #endif diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 808633f..a31370b 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -21,6 +21,10 @@ #include <mach/hardware.h> #include <mach/i2c.h> #include <mach/irqs.h> +#include <mach/cputype.h> +#include <mach/mux.h> + +#define DAVINCI_I2C_BASE 0x01C21000 static struct resource i2c_resources[] = { { @@ -43,6 +47,9 @@ static struct platform_device davinci_i2c_device = { void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) { + if (cpu_is_davinci_dm644x()) + davinci_cfg_reg(DM644X_I2C); + davinci_i2c_device.dev.platform_data = pdata; (void) platform_device_register(&davinci_i2c_device); } diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c new file mode 100644 index 0000000..d428ef1 --- /dev/null +++ b/arch/arm/mach-davinci/dm644x.c @@ -0,0 +1,461 @@ +/* + * TI DaVinci DM644x chip specific setup + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/platform_device.h> + +#include <mach/dm644x.h> +#include <mach/clock.h> +#include <mach/cputype.h> +#include <mach/edma.h> +#include <mach/irqs.h> +#include <mach/psc.h> +#include <mach/mux.h> + +#include "clock.h" +#include "mux.h" + +/* + * Device specific clocks + */ +#define DM644X_REF_FREQ 27000000 + +static struct pll_data pll1_data = { + .num = 1, + .phys_base = DAVINCI_PLL1_BASE, +}; + +static struct pll_data pll2_data = { + .num = 2, + .phys_base = DAVINCI_PLL2_BASE, +}; + +static struct clk ref_clk = { + .name = "ref_clk", + .rate = DM644X_REF_FREQ, +}; + +static struct clk pll1_clk = { + .name = "pll1", + .parent = &ref_clk, + .pll_data = &pll1_data, + .flags = CLK_PLL, +}; + +static struct clk pll1_sysclk1 = { + .name = "pll1_sysclk1", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk pll1_sysclk2 = { + .name = "pll1_sysclk2", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll1_sysclk3 = { + .name = "pll1_sysclk3", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll1_sysclk5 = { + .name = "pll1_sysclk5", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll1_aux_clk = { + .name = "pll1_aux_clk", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll1_sysclkbp = { + .name = "pll1_sysclkbp", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV +}; + +static struct clk pll2_clk = { + .name = "pll2", + .parent = &ref_clk, + .pll_data = &pll2_data, + .flags = CLK_PLL, +}; + +static struct clk pll2_sysclk1 = { + .name = "pll2_sysclk1", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk pll2_sysclk2 = { + .name = "pll2_sysclk2", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll2_sysclkbp = { + .name = "pll2_sysclkbp", + .parent = &pll2_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV +}; + +static struct clk dsp_clk = { + .name = "dsp", + .parent = &pll1_sysclk1, + .lpsc = DAVINCI_LPSC_GEM, + .flags = PSC_DSP, + .usecount = 1, /* REVISIT how to disable? */ +}; + +static struct clk arm_clk = { + .name = "arm", + .parent = &pll1_sysclk2, + .lpsc = DAVINCI_LPSC_ARM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk vicp_clk = { + .name = "vicp", + .parent = &pll1_sysclk2, + .lpsc = DAVINCI_LPSC_IMCOP, + .flags = PSC_DSP, + .usecount = 1, /* REVISIT how to disable? */ +}; + +static struct clk vpss_master_clk = { + .name = "vpss_master", + .parent = &pll1_sysclk3, + .lpsc = DAVINCI_LPSC_VPSSMSTR, + .flags = CLK_PSC, +}; + +static struct clk vpss_slave_clk = { + .name = "vpss_slave", + .parent = &pll1_sysclk3, + .lpsc = DAVINCI_LPSC_VPSSSLV, +}; + +static struct clk uart0_clk = { + .name = "uart0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_UART0, +}; + +static struct clk uart1_clk = { + .name = "uart1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_UART1, +}; + +static struct clk uart2_clk = { + .name = "uart2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_UART2, +}; + +static struct clk emac_clk = { + .name = "emac", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, +}; + +static struct clk i2c_clk = { + .name = "i2c", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_I2C, +}; + +static struct clk ide_clk = { + .name = "ide", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_ATA, +}; + +static struct clk asp_clk = { + .name = "asp0", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_McBSP, +}; + +static struct clk mmcsd_clk = { + .name = "mmcsd", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_MMC_SD, +}; + +static struct clk spi_clk = { + .name = "spi", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_SPI, +}; + +static struct clk gpio_clk = { + .name = "gpio", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_GPIO, +}; + +static struct clk usb_clk = { + .name = "usb", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_USB, +}; + +static struct clk vlynq_clk = { + .name = "vlynq", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_VLYNQ, +}; + +static struct clk aemif_clk = { + .name = "aemif", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_AEMIF, +}; + +static struct clk pwm0_clk = { + .name = "pwm0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM0, +}; + +static struct clk pwm1_clk = { + .name = "pwm1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM1, +}; + +static struct clk pwm2_clk = { + .name = "pwm2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM2, +}; + +static struct clk timer0_clk = { + .name = "timer0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER0, +}; + +static struct clk timer1_clk = { + .name = "timer1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER1, +}; + +static struct clk timer2_clk = { + .name = "timer2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER2, + .usecount = 1, /* REVISIT: why cant' this be disabled? */ +}; + +struct davinci_clk dm644x_clks[] = { + CLK(NULL, "ref", &ref_clk), + CLK(NULL, "pll1", &pll1_clk), + CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), + CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), + CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), + CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), + CLK(NULL, "pll1_aux", &pll1_aux_clk), + CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), + CLK(NULL, "pll2", &pll2_clk), + CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), + CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), + CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), + CLK(NULL, "dsp", &dsp_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "vicp", &vicp_clk), + CLK(NULL, "vpss_master", &vpss_master_clk), + CLK(NULL, "vpss_slave", &vpss_slave_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "uart0", &uart0_clk), + CLK(NULL, "uart1", &uart1_clk), + CLK(NULL, "uart2", &uart2_clk), + CLK("davinci_emac.1", NULL, &emac_clk), + CLK("i2c_davinci.1", NULL, &i2c_clk), + CLK("palm_bk3710", NULL, &ide_clk), + CLK("soc-audio.0", NULL, &asp_clk), + CLK("davinci_mmc.0", NULL, &mmcsd_clk), + CLK(NULL, "spi", &spi_clk), + CLK(NULL, "gpio", &gpio_clk), + CLK(NULL, "usb", &usb_clk), + CLK(NULL, "vlynq", &vlynq_clk), + CLK(NULL, "aemif", &aemif_clk), + CLK(NULL, "pwm0", &pwm0_clk), + CLK(NULL, "pwm1", &pwm1_clk), + CLK(NULL, "pwm2", &pwm2_clk), + CLK(NULL, "timer0", &timer0_clk), + CLK(NULL, "timer1", &timer1_clk), + CLK("watchdog", NULL, &timer2_clk), + CLK(NULL, NULL, NULL), +}; + +#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE) + +static struct resource dm644x_emac_resources[] = { + { + .start = DM644X_EMAC_BASE, + .end = DM644X_EMAC_BASE + 0x47ff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_EMACINT, + .end = IRQ_EMACINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dm644x_emac_device = { + .name = "davinci_emac", + .id = 1, + .num_resources = ARRAY_SIZE(dm644x_emac_resources), + .resource = dm644x_emac_resources, +}; + +#endif + +/* + * Device specific mux setup + * + * soc description mux mode mode mux dbg + * reg offset mask mode + */ +static const struct mux_config dm644x_pins[] = { +MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true) +MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true) +MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) + +MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true) + +MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true) + +MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false) + +MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false) + +MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false) + +MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true) +MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true) + +MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false) + +MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false) + +MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false) + +MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false) +MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false) +MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false) + +MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true) + +MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true) + +MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true) +MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false) +MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false) +MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true) + +MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true) + +MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true) +MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) +}; + + +/*----------------------------------------------------------------------*/ + +static const s8 dma_chan_dm644x_no_event[] = { + 0, 1, 12, 13, 14, + 15, 25, 30, 31, 45, + 46, 47, 55, 56, 57, + 58, 59, 60, 61, 62, + 63, + -1 +}; + +static struct edma_soc_info dm644x_edma_info = { + .n_channel = 64, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .noevent = dma_chan_dm644x_no_event, +}; + +static struct resource edma_resources[] = { + { + .name = "edma_cc", + .start = 0x01c00000, + .end = 0x01c00000 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = 0x01c10000, + .end = 0x01c10000 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = 0x01c10400, + .end = 0x01c10400 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_CCINT0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_CCERRINT, + .flags = IORESOURCE_IRQ, + }, + /* not using TC*_ERR */ +}; + +static struct platform_device dm644x_edma_device = { + .name = "edma", + .id = -1, + .dev.platform_data = &dm644x_edma_info, + .num_resources = ARRAY_SIZE(edma_resources), + .resource = edma_resources, +}; + +/*----------------------------------------------------------------------*/ +void __init dm644x_init(void) +{ + davinci_clk_init(dm644x_clks); + davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins)); +} + +static int __init dm644x_init_devices(void) +{ + if (!cpu_is_davinci_dm644x()) + return 0; + + platform_device_register(&dm644x_edma_device); + return 0; +} +postcore_initcall(dm644x_init_devices); diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c new file mode 100644 index 0000000..15e9eb1 --- /dev/null +++ b/arch/arm/mach-davinci/dma.c @@ -0,0 +1,1135 @@ +/* + * EDMA3 support for DaVinci + * + * Copyright (C) 2006-2009 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> +#include <linux/compiler.h> +#include <linux/io.h> + +#include <mach/cputype.h> +#include <mach/memory.h> +#include <mach/hardware.h> +#include <mach/irqs.h> +#include <mach/edma.h> +#include <mach/mux.h> + + +/* Offsets matching "struct edmacc_param" */ +#define PARM_OPT 0x00 +#define PARM_SRC 0x04 +#define PARM_A_B_CNT 0x08 +#define PARM_DST 0x0c +#define PARM_SRC_DST_BIDX 0x10 +#define PARM_LINK_BCNTRLD 0x14 +#define PARM_SRC_DST_CIDX 0x18 +#define PARM_CCNT 0x1c + +#define PARM_SIZE 0x20 + +/* Offsets for EDMA CC global channel registers and their shadows */ +#define SH_ER 0x00 /* 64 bits */ +#define SH_ECR 0x08 /* 64 bits */ +#define SH_ESR 0x10 /* 64 bits */ +#define SH_CER 0x18 /* 64 bits */ +#define SH_EER 0x20 /* 64 bits */ +#define SH_EECR 0x28 /* 64 bits */ +#define SH_EESR 0x30 /* 64 bits */ +#define SH_SER 0x38 /* 64 bits */ +#define SH_SECR 0x40 /* 64 bits */ +#define SH_IER 0x50 /* 64 bits */ +#define SH_IECR 0x58 /* 64 bits */ +#define SH_IESR 0x60 /* 64 bits */ +#define SH_IPR 0x68 /* 64 bits */ +#define SH_ICR 0x70 /* 64 bits */ +#define SH_IEVAL 0x78 +#define SH_QER 0x80 +#define SH_QEER 0x84 +#define SH_QEECR 0x88 +#define SH_QEESR 0x8c +#define SH_QSER 0x90 +#define SH_QSECR 0x94 +#define SH_SIZE 0x200 + +/* Offsets for EDMA CC global registers */ +#define EDMA_REV 0x0000 +#define EDMA_CCCFG 0x0004 +#define EDMA_QCHMAP 0x0200 /* 8 registers */ +#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ +#define EDMA_QDMAQNUM 0x0260 +#define EDMA_QUETCMAP 0x0280 +#define EDMA_QUEPRI 0x0284 +#define EDMA_EMR 0x0300 /* 64 bits */ +#define EDMA_EMCR 0x0308 /* 64 bits */ +#define EDMA_QEMR 0x0310 +#define EDMA_QEMCR 0x0314 +#define EDMA_CCERR 0x0318 +#define EDMA_CCERRCLR 0x031c +#define EDMA_EEVAL 0x0320 +#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ +#define EDMA_QRAE 0x0380 /* 4 registers */ +#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ +#define EDMA_QSTAT 0x0600 /* 2 registers */ +#define EDMA_QWMTHRA 0x0620 +#define EDMA_QWMTHRB 0x0624 +#define EDMA_CCSTAT 0x0640 + +#define EDMA_M 0x1000 /* global channel registers */ +#define EDMA_ECR 0x1008 +#define EDMA_ECRH 0x100C +#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ +#define EDMA_PARM 0x4000 /* 128 param entries */ + +#define DAVINCI_DMA_3PCC_BASE 0x01C00000 + +#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) + +#define EDMA_MAX_DMACH 64 +#define EDMA_MAX_PARAMENTRY 512 +#define EDMA_MAX_EVQUE 2 /* FIXME too small */ + + +/*****************************************************************************/ + +static void __iomem *edmacc_regs_base; + +static inline unsigned int edma_read(int offset) +{ + return (unsigned int)__raw_readl(edmacc_regs_base + offset); +} + +static inline void edma_write(int offset, int val) +{ + __raw_writel(val, edmacc_regs_base + offset); +} +static inline void edma_modify(int offset, unsigned and, unsigned or) +{ + unsigned val = edma_read(offset); + val &= and; + val |= or; + edma_write(offset, val); +} +static inline void edma_and(int offset, unsigned and) +{ + unsigned val = edma_read(offset); + val &= and; + edma_write(offset, val); +} +static inline void edma_or(int offset, unsigned or) +{ + unsigned val = edma_read(offset); + val |= or; + edma_write(offset, val); +} +static inline unsigned int edma_read_array(int offset, int i) +{ + return edma_read(offset + (i << 2)); +} +static inline void edma_write_array(int offset, int i, unsigned val) +{ + edma_write(offset + (i << 2), val); +} +static inline void edma_modify_array(int offset, int i, + unsigned and, unsigned or) +{ + edma_modify(offset + (i << 2), and, or); +} +static inline void edma_or_array(int offset, int i, unsigned or) +{ + edma_or(offset + (i << 2), or); +} +static inline void edma_or_array2(int offset, int i, int j, unsigned or) +{ + edma_or(offset + ((i*2 + j) << 2), or); +} +static inline void edma_write_array2(int offset, int i, int j, unsigned val) +{ + edma_write(offset + ((i*2 + j) << 2), val); +} +static inline unsigned int edma_shadow0_read(int offset) +{ + return edma_read(EDMA_SHADOW0 + offset); +} +static inline unsigned int edma_shadow0_read_array(int offset, int i) +{ + return edma_read(EDMA_SHADOW0 + offset + (i << 2)); +} +static inline void edma_shadow0_write(int offset, unsigned val) +{ + edma_write(EDMA_SHADOW0 + offset, val); +} +static inline void edma_shadow0_write_array(int offset, int i, unsigned val) +{ + edma_write(EDMA_SHADOW0 + offset + (i << 2), val); +} +static inline unsigned int edma_parm_read(int offset, int param_no) +{ + return edma_read(EDMA_PARM + offset + (param_no << 5)); +} +static inline void edma_parm_write(int offset, int param_no, unsigned val) +{ + edma_write(EDMA_PARM + offset + (param_no << 5), val); +} +static inline void edma_parm_modify(int offset, int param_no, + unsigned and, unsigned or) +{ + edma_modify(EDMA_PARM + offset + (param_no << 5), and, or); +} +static inline void edma_parm_and(int offset, int param_no, unsigned and) +{ + edma_and(EDMA_PARM + offset + (param_no << 5), and); +} +static inline void edma_parm_or(int offset, int param_no, unsigned or) +{ + edma_or(EDMA_PARM + offset + (param_no << 5), or); +} + +/*****************************************************************************/ + +/* actual number of DMA channels and slots on this silicon */ +static unsigned num_channels; +static unsigned num_slots; + +static struct dma_interrupt_data { + void (*callback)(unsigned channel, unsigned short ch_status, + void *data); + void *data; +} intr_data[EDMA_MAX_DMACH]; + +/* The edma_inuse bit for each PaRAM slot is clear unless the + * channel is in use ... by ARM or DSP, for QDMA, or whatever. + */ +static DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); + +/* The edma_noevent bit for each channel is clear unless + * it doesn't trigger DMA events on this platform. It uses a + * bit of SOC-specific initialization code. + */ +static DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH); + +/* dummy param set used to (re)initialize parameter RAM slots */ +static const struct edmacc_param dummy_paramset = { + .link_bcntrld = 0xffff, + .ccnt = 1, +}; + +static const int __initconst +queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = { +/* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {-1, -1} +}; + +static const int __initconst +queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = { + /* {event queue no, Priority} */ + {0, 3}, + {1, 7}, + {-1, -1} +}; + +/*****************************************************************************/ + +static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no) +{ + int bit = (ch_no & 0x7) * 4; + + /* default to low priority queue */ + if (queue_no == EVENTQ_DEFAULT) + queue_no = EVENTQ_1; + + queue_no &= 7; + edma_modify_array(EDMA_DMAQNUM, (ch_no >> 3), + ~(0x7 << bit), queue_no << bit); +} + +static void __init map_queue_tc(int queue_no, int tc_no) +{ + int bit = queue_no * 4; + edma_modify(EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); +} + +static void __init assign_priority_to_queue(int queue_no, int priority) +{ + int bit = queue_no * 4; + edma_modify(EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); +} + +static inline void +setup_dma_interrupt(unsigned lch, + void (*callback)(unsigned channel, u16 ch_status, void *data), + void *data) +{ + if (!callback) { + edma_shadow0_write_array(SH_IECR, lch >> 5, + (1 << (lch & 0x1f))); + } + + intr_data[lch].callback = callback; + intr_data[lch].data = data; + + if (callback) { + edma_shadow0_write_array(SH_ICR, lch >> 5, + (1 << (lch & 0x1f))); + edma_shadow0_write_array(SH_IESR, lch >> 5, + (1 << (lch & 0x1f))); + } +} + +/****************************************************************************** + * + * DMA interrupt handler + * + *****************************************************************************/ +static irqreturn_t dma_irq_handler(int irq, void *data) +{ + int i; + unsigned int cnt = 0; + + dev_dbg(data, "dma_irq_handler\n"); + + if ((edma_shadow0_read_array(SH_IPR, 0) == 0) + && (edma_shadow0_read_array(SH_IPR, 1) == 0)) + return IRQ_NONE; + + while (1) { + int j; + if (edma_shadow0_read_array(SH_IPR, 0)) + j = 0; + else if (edma_shadow0_read_array(SH_IPR, 1)) + j = 1; + else + break; + dev_dbg(data, "IPR%d %08x\n", j, + edma_shadow0_read_array(SH_IPR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + if (edma_shadow0_read_array(SH_IPR, j) & (1 << i)) { + /* Clear the corresponding IPR bits */ + edma_shadow0_write_array(SH_ICR, j, (1 << i)); + if (intr_data[k].callback) { + intr_data[k].callback(k, DMA_COMPLETE, + intr_data[k].data); + } + } + } + cnt++; + if (cnt > 10) + break; + } + edma_shadow0_write(SH_IEVAL, 1); + return IRQ_HANDLED; +} + +/****************************************************************************** + * + * DMA error interrupt handler + * + *****************************************************************************/ +static irqreturn_t dma_ccerr_handler(int irq, void *data) +{ + int i; + unsigned int cnt = 0; + + dev_dbg(data, "dma_ccerr_handler\n"); + + if ((edma_read_array(EDMA_EMR, 0) == 0) && + (edma_read_array(EDMA_EMR, 1) == 0) && + (edma_read(EDMA_QEMR) == 0) && (edma_read(EDMA_CCERR) == 0)) + return IRQ_NONE; + + while (1) { + int j = -1; + if (edma_read_array(EDMA_EMR, 0)) + j = 0; + else if (edma_read_array(EDMA_EMR, 1)) + j = 1; + if (j >= 0) { + dev_dbg(data, "EMR%d %08x\n", j, + edma_read_array(EDMA_EMR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + if (edma_read_array(EDMA_EMR, j) & (1 << i)) { + /* Clear the corresponding EMR bits */ + edma_write_array(EDMA_EMCR, j, 1 << i); + /* Clear any SER */ + edma_shadow0_write_array(SH_SECR, j, + (1 << i)); + if (intr_data[k].callback) { + intr_data[k].callback(k, + DMA_CC_ERROR, + intr_data + [k].data); + } + } + } + } else if (edma_read(EDMA_QEMR)) { + dev_dbg(data, "QEMR %02x\n", + edma_read(EDMA_QEMR)); + for (i = 0; i < 8; i++) { + if (edma_read(EDMA_QEMR) & (1 << i)) { + /* Clear the corresponding IPR bits */ + edma_write(EDMA_QEMCR, 1 << i); + edma_shadow0_write(SH_QSECR, (1 << i)); + + /* NOTE: not reported!! */ + } + } + } else if (edma_read(EDMA_CCERR)) { + dev_dbg(data, "CCERR %08x\n", + edma_read(EDMA_CCERR)); + /* FIXME: CCERR.BIT(16) ignored! much better + * to just write CCERRCLR with CCERR value... + */ + for (i = 0; i < 8; i++) { + if (edma_read(EDMA_CCERR) & (1 << i)) { + /* Clear the corresponding IPR bits */ + edma_write(EDMA_CCERRCLR, 1 << i); + + /* NOTE: not reported!! */ + } + } + } + if ((edma_read_array(EDMA_EMR, 0) == 0) + && (edma_read_array(EDMA_EMR, 1) == 0) + && (edma_read(EDMA_QEMR) == 0) + && (edma_read(EDMA_CCERR) == 0)) { + break; + } + cnt++; + if (cnt > 10) + break; + } + edma_write(EDMA_EEVAL, 1); + return IRQ_HANDLED; +} + +/****************************************************************************** + * + * Transfer controller error interrupt handlers + * + *****************************************************************************/ + +#define tc_errs_handled false /* disabled as long as they're NOPs */ + +static irqreturn_t dma_tc0err_handler(int irq, void *data) +{ + dev_dbg(data, "dma_tc0err_handler\n"); + return IRQ_HANDLED; +} + +static irqreturn_t dma_tc1err_handler(int irq, void *data) +{ + dev_dbg(data, "dma_tc1err_handler\n"); + return IRQ_HANDLED; +} + +/*-----------------------------------------------------------------------*/ + +/* Resource alloc/free: dma channels, parameter RAM slots */ + +/** + * edma_alloc_channel - allocate DMA channel and paired parameter RAM + * @channel: specific channel to allocate; negative for "any unmapped channel" + * @callback: optional; to be issued on DMA completion or errors + * @data: passed to callback + * @eventq_no: an EVENTQ_* constant, used to choose which Transfer + * Controller (TC) executes requests using this channel. Use + * EVENTQ_DEFAULT unless you really need a high priority queue. + * + * This allocates a DMA channel and its associated parameter RAM slot. + * The parameter RAM is initialized to hold a dummy transfer. + * + * Normal use is to pass a specific channel number as @channel, to make + * use of hardware events mapped to that channel. When the channel will + * be used only for software triggering or event chaining, channels not + * mapped to hardware events (or mapped to unused events) are preferable. + * + * DMA transfers start from a channel using edma_start(), or by + * chaining. When the transfer described in that channel's parameter RAM + * slot completes, that slot's data may be reloaded through a link. + * + * DMA errors are only reported to the @callback associated with the + * channel driving that transfer, but transfer completion callbacks can + * be sent to another channel under control of the TCC field in + * the option word of the transfer's parameter RAM set. Drivers must not + * use DMA transfer completion callbacks for channels they did not allocate. + * (The same applies to TCC codes used in transfer chaining.) + * + * Returns the number of the channel, else negative errno. + */ +int edma_alloc_channel(int channel, + void (*callback)(unsigned channel, u16 ch_status, void *data), + void *data, + enum dma_event_q eventq_no) +{ + if (channel < 0) { + channel = 0; + for (;;) { + channel = find_next_bit(edma_noevent, + num_channels, channel); + if (channel == num_channels) + return -ENOMEM; + if (!test_and_set_bit(channel, edma_inuse)) + break; + channel++; + } + } else if (channel >= num_channels) { + return -EINVAL; + } else if (test_and_set_bit(channel, edma_inuse)) { + return -EBUSY; + } + + /* ensure access through shadow region 0 */ + edma_or_array2(EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); + + /* ensure no events are pending */ + edma_stop(channel); + memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel), + &dummy_paramset, PARM_SIZE); + + if (callback) + setup_dma_interrupt(channel, callback, data); + + map_dmach_queue(channel, eventq_no); + + return channel; +} +EXPORT_SYMBOL(edma_alloc_channel); + + +/** + * edma_free_channel - deallocate DMA channel + * @channel: dma channel returned from edma_alloc_channel() + * + * This deallocates the DMA channel and associated parameter RAM slot + * allocated by edma_alloc_channel(). + * + * Callers are responsible for ensuring the channel is inactive, and + * will not be reactivated by linking, chaining, or software calls to + * edma_start(). + */ +void edma_free_channel(unsigned channel) +{ + if (channel >= num_channels) + return; + + setup_dma_interrupt(channel, NULL, NULL); + /* REVISIT should probably take out of shadow region 0 */ + + memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel), + &dummy_paramset, PARM_SIZE); + clear_bit(channel, edma_inuse); +} +EXPORT_SYMBOL(edma_free_channel); + +/** + * edma_alloc_slot - allocate DMA parameter RAM + * @slot: specific slot to allocate; negative for "any unused slot" + * + * This allocates a parameter RAM slot, initializing it to hold a + * dummy transfer. Slots allocated using this routine have not been + * mapped to a hardware DMA channel, and will normally be used by + * linking to them from a slot associated with a DMA channel. + * + * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific + * slots may be allocated on behalf of DSP firmware. + * + * Returns the number of the slot, else negative errno. + */ +int edma_alloc_slot(int slot) +{ + if (slot < 0) { + slot = num_channels; + for (;;) { + slot = find_next_zero_bit(edma_inuse, + num_slots, slot); + if (slot == num_slots) + return -ENOMEM; + if (!test_and_set_bit(slot, edma_inuse)) + break; + } + } else if (slot < num_channels || slot >= num_slots) { + return -EINVAL; + } else if (test_and_set_bit(slot, edma_inuse)) { + return -EBUSY; + } + + memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), + &dummy_paramset, PARM_SIZE); + + return slot; +} +EXPORT_SYMBOL(edma_alloc_slot); + +/** + * edma_free_slot - deallocate DMA parameter RAM + * @slot: parameter RAM slot returned from edma_alloc_slot() + * + * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). + * Callers are responsible for ensuring the slot is inactive, and will + * not be activated. + */ +void edma_free_slot(unsigned slot) +{ + if (slot < num_channels || slot >= num_slots) + return; + + memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), + &dummy_paramset, PARM_SIZE); + clear_bit(slot, edma_inuse); +} +EXPORT_SYMBOL(edma_free_slot); + +/*-----------------------------------------------------------------------*/ + +/* Parameter RAM operations (i) -- read/write partial slots */ + +/** + * edma_set_src - set initial DMA source address in parameter RAM slot + * @slot: parameter RAM slot being configured + * @src_port: physical address of source (memory, controller FIFO, etc) + * @addressMode: INCR, except in very rare cases + * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the + * width to use when addressing the fifo (e.g. W8BIT, W32BIT) + * + * Note that the source address is modified during the DMA transfer + * according to edma_set_src_index(). + */ +void edma_set_src(unsigned slot, dma_addr_t src_port, + enum address_mode mode, enum fifo_width width) +{ + if (slot < num_slots) { + unsigned int i = edma_parm_read(PARM_OPT, slot); + + if (mode) { + /* set SAM and program FWID */ + i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); + } else { + /* clear SAM */ + i &= ~SAM; + } + edma_parm_write(PARM_OPT, slot, i); + + /* set the source port address + in source register of param structure */ + edma_parm_write(PARM_SRC, slot, src_port); + } +} +EXPORT_SYMBOL(edma_set_src); + +/** + * edma_set_dest - set initial DMA destination address in parameter RAM slot + * @slot: parameter RAM slot being configured + * @dest_port: physical address of destination (memory, controller FIFO, etc) + * @addressMode: INCR, except in very rare cases + * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the + * width to use when addressing the fifo (e.g. W8BIT, W32BIT) + * + * Note that the destination address is modified during the DMA transfer + * according to edma_set_dest_index(). + */ +void edma_set_dest(unsigned slot, dma_addr_t dest_port, + enum address_mode mode, enum fifo_width width) +{ + if (slot < num_slots) { + unsigned int i = edma_parm_read(PARM_OPT, slot); + + if (mode) { + /* set DAM and program FWID */ + i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); + } else { + /* clear DAM */ + i &= ~DAM; + } + edma_parm_write(PARM_OPT, slot, i); + /* set the destination port address + in dest register of param structure */ + edma_parm_write(PARM_DST, slot, dest_port); + } +} +EXPORT_SYMBOL(edma_set_dest); + +/** + * edma_get_position - returns the current transfer points + * @slot: parameter RAM slot being examined + * @src: pointer to source port position + * @dst: pointer to destination port position + * + * Returns current source and destination addresses for a particular + * parameter RAM slot. Its channel should not be active when this is called. + */ +void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst) +{ + struct edmacc_param temp; + + edma_read_slot(slot, &temp); + if (src != NULL) + *src = temp.src; + if (dst != NULL) + *dst = temp.dst; +} +EXPORT_SYMBOL(edma_get_position); + +/** + * edma_set_src_index - configure DMA source address indexing + * @slot: parameter RAM slot being configured + * @src_bidx: byte offset between source arrays in a frame + * @src_cidx: byte offset between source frames in a block + * + * Offsets are specified to support either contiguous or discontiguous + * memory transfers, or repeated access to a hardware register, as needed. + * When accessing hardware registers, both offsets are normally zero. + */ +void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) +{ + if (slot < num_slots) { + edma_parm_modify(PARM_SRC_DST_BIDX, slot, + 0xffff0000, src_bidx); + edma_parm_modify(PARM_SRC_DST_CIDX, slot, + 0xffff0000, src_cidx); + } +} +EXPORT_SYMBOL(edma_set_src_index); + +/** + * edma_set_dest_index - configure DMA destination address indexing + * @slot: parameter RAM slot being configured + * @dest_bidx: byte offset between destination arrays in a frame + * @dest_cidx: byte offset between destination frames in a block + * + * Offsets are specified to support either contiguous or discontiguous + * memory transfers, or repeated access to a hardware register, as needed. + * When accessing hardware registers, both offsets are normally zero. + */ +void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) +{ + if (slot < num_slots) { + edma_parm_modify(PARM_SRC_DST_BIDX, slot, + 0x0000ffff, dest_bidx << 16); + edma_parm_modify(PARM_SRC_DST_CIDX, slot, + 0x0000ffff, dest_cidx << 16); + } +} +EXPORT_SYMBOL(edma_set_dest_index); + +/** + * edma_set_transfer_params - configure DMA transfer parameters + * @slot: parameter RAM slot being configured + * @acnt: how many bytes per array (at least one) + * @bcnt: how many arrays per frame (at least one) + * @ccnt: how many frames per block (at least one) + * @bcnt_rld: used only for A-Synchronized transfers; this specifies + * the value to reload into bcnt when it decrements to zero + * @sync_mode: ASYNC or ABSYNC + * + * See the EDMA3 documentation to understand how to configure and link + * transfers using the fields in PaRAM slots. If you are not doing it + * all at once with edma_write_slot(), you will use this routine + * plus two calls each for source and destination, setting the initial + * address and saying how to index that address. + * + * An example of an A-Synchronized transfer is a serial link using a + * single word shift register. In that case, @acnt would be equal to + * that word size; the serial controller issues a DMA synchronization + * event to transfer each word, and memory access by the DMA transfer + * controller will be word-at-a-time. + * + * An example of an AB-Synchronized transfer is a device using a FIFO. + * In that case, @acnt equals the FIFO width and @bcnt equals its depth. + * The controller with the FIFO issues DMA synchronization events when + * the FIFO threshold is reached, and the DMA transfer controller will + * transfer one frame to (or from) the FIFO. It will probably use + * efficient burst modes to access memory. + */ +void edma_set_transfer_params(unsigned slot, + u16 acnt, u16 bcnt, u16 ccnt, + u16 bcnt_rld, enum sync_dimension sync_mode) +{ + if (slot < num_slots) { + edma_parm_modify(PARM_LINK_BCNTRLD, slot, + 0x0000ffff, bcnt_rld << 16); + if (sync_mode == ASYNC) + edma_parm_and(PARM_OPT, slot, ~SYNCDIM); + else + edma_parm_or(PARM_OPT, slot, SYNCDIM); + /* Set the acount, bcount, ccount registers */ + edma_parm_write(PARM_A_B_CNT, slot, (bcnt << 16) | acnt); + edma_parm_write(PARM_CCNT, slot, ccnt); + } +} +EXPORT_SYMBOL(edma_set_transfer_params); + +/** + * edma_link - link one parameter RAM slot to another + * @from: parameter RAM slot originating the link + * @to: parameter RAM slot which is the link target + * + * The originating slot should not be part of any active DMA transfer. + */ +void edma_link(unsigned from, unsigned to) +{ + if (from >= num_slots) + return; + if (to >= num_slots) + return; + edma_parm_modify(PARM_LINK_BCNTRLD, from, 0xffff0000, PARM_OFFSET(to)); +} +EXPORT_SYMBOL(edma_link); + +/** + * edma_unlink - cut link from one parameter RAM slot + * @from: parameter RAM slot originating the link + * + * The originating slot should not be part of any active DMA transfer. + * Its link is set to 0xffff. + */ +void edma_unlink(unsigned from) +{ + if (from >= num_slots) + return; + edma_parm_or(PARM_LINK_BCNTRLD, from, 0xffff); +} +EXPORT_SYMBOL(edma_unlink); + +/*-----------------------------------------------------------------------*/ + +/* Parameter RAM operations (ii) -- read/write whole parameter sets */ + +/** + * edma_write_slot - write parameter RAM data for slot + * @slot: number of parameter RAM slot being modified + * @param: data to be written into parameter RAM slot + * + * Use this to assign all parameters of a transfer at once. This + * allows more efficient setup of transfers than issuing multiple + * calls to set up those parameters in small pieces, and provides + * complete control over all transfer options. + */ +void edma_write_slot(unsigned slot, const struct edmacc_param *param) +{ + if (slot >= num_slots) + return; + memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), param, PARM_SIZE); +} +EXPORT_SYMBOL(edma_write_slot); + +/** + * edma_read_slot - read parameter RAM data from slot + * @slot: number of parameter RAM slot being copied + * @param: where to store copy of parameter RAM data + * + * Use this to read data from a parameter RAM slot, perhaps to + * save them as a template for later reuse. + */ +void edma_read_slot(unsigned slot, struct edmacc_param *param) +{ + if (slot >= num_slots) + return; + memcpy_fromio(param, edmacc_regs_base + PARM_OFFSET(slot), PARM_SIZE); +} +EXPORT_SYMBOL(edma_read_slot); + +/*-----------------------------------------------------------------------*/ + +/* Various EDMA channel control operations */ + +/** + * edma_pause - pause dma on a channel + * @channel: on which edma_start() has been called + * + * This temporarily disables EDMA hardware events on the specified channel, + * preventing them from triggering new transfers on its behalf + */ +void edma_pause(unsigned channel) +{ + if (channel < num_channels) { + unsigned int mask = (1 << (channel & 0x1f)); + + edma_shadow0_write_array(SH_EECR, channel >> 5, mask); + } +} +EXPORT_SYMBOL(edma_pause); + +/** + * edma_resume - resumes dma on a paused channel + * @channel: on which edma_pause() has been called + * + * This re-enables EDMA hardware events on the specified channel. + */ +void edma_resume(unsigned channel) +{ + if (channel < num_channels) { + unsigned int mask = (1 << (channel & 0x1f)); + + edma_shadow0_write_array(SH_EESR, channel >> 5, mask); + } +} +EXPORT_SYMBOL(edma_resume); + +/** + * edma_start - start dma on a channel + * @channel: channel being activated + * + * Channels with event associations will be triggered by their hardware + * events, and channels without such associations will be triggered by + * software. (At this writing there is no interface for using software + * triggers except with channels that don't support hardware triggers.) + * + * Returns zero on success, else negative errno. + */ +int edma_start(unsigned channel) +{ + if (channel < num_channels) { + int j = channel >> 5; + unsigned int mask = (1 << (channel & 0x1f)); + + /* EDMA channels without event association */ + if (test_bit(channel, edma_noevent)) { + pr_debug("EDMA: ESR%d %08x\n", j, + edma_shadow0_read_array(SH_ESR, j)); + edma_shadow0_write_array(SH_ESR, j, mask); + return 0; + } + + /* EDMA channel with event association */ + pr_debug("EDMA: ER%d %08x\n", j, + edma_shadow0_read_array(SH_ER, j)); + /* Clear any pending error */ + edma_write_array(EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(SH_SECR, j, mask); + edma_shadow0_write_array(SH_EESR, j, mask); + pr_debug("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(SH_EER, j)); + return 0; + } + + return -EINVAL; +} +EXPORT_SYMBOL(edma_start); + +/** + * edma_stop - stops dma on the channel passed + * @channel: channel being deactivated + * + * When @lch is a channel, any active transfer is paused and + * all pending hardware events are cleared. The current transfer + * may not be resumed, and the channel's Parameter RAM should be + * reinitialized before being reused. + */ +void edma_stop(unsigned channel) +{ + if (channel < num_channels) { + int j = channel >> 5; + unsigned int mask = (1 << (channel & 0x1f)); + + edma_shadow0_write_array(SH_EECR, j, mask); + edma_shadow0_write_array(SH_ECR, j, mask); + edma_shadow0_write_array(SH_SECR, j, mask); + edma_write_array(EDMA_EMCR, j, mask); + + pr_debug("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(SH_EER, j)); + + /* REVISIT: consider guarding against inappropriate event + * chaining by overwriting with dummy_paramset. + */ + } +} +EXPORT_SYMBOL(edma_stop); + +/****************************************************************************** + * + * It cleans ParamEntry qand bring back EDMA to initial state if media has + * been removed before EDMA has finished.It is usedful for removable media. + * Arguments: + * ch_no - channel no + * + * Return: zero on success, or corresponding error no on failure + * + * FIXME this should not be needed ... edma_stop() should suffice. + * + *****************************************************************************/ + +void edma_clean_channel(unsigned channel) +{ + if (channel < num_channels) { + int j = (channel >> 5); + unsigned int mask = 1 << (channel & 0x1f); + + pr_debug("EDMA: EMR%d %08x\n", j, + edma_read_array(EDMA_EMR, j)); + edma_shadow0_write_array(SH_ECR, j, mask); + /* Clear the corresponding EMR bits */ + edma_write_array(EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(SH_SECR, j, mask); + edma_write(EDMA_CCERRCLR, (1 << 16) | 0x3); + } +} +EXPORT_SYMBOL(edma_clean_channel); + +/* + * edma_clear_event - clear an outstanding event on the DMA channel + * Arguments: + * channel - channel number + */ +void edma_clear_event(unsigned channel) +{ + if (channel >= num_channels) + return; + if (channel < 32) + edma_write(EDMA_ECR, 1 << channel); + else + edma_write(EDMA_ECRH, 1 << (channel - 32)); +} +EXPORT_SYMBOL(edma_clear_event); + +/*-----------------------------------------------------------------------*/ + +static int __init edma_probe(struct platform_device *pdev) +{ + struct edma_soc_info *info = pdev->dev.platform_data; + int i; + int status; + const s8 *noevent; + int irq = 0, err_irq = 0; + struct resource *r; + resource_size_t len; + + if (!info) + return -ENODEV; + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma_cc"); + if (!r) + return -ENODEV; + + len = r->end - r->start + 1; + + r = request_mem_region(r->start, len, r->name); + if (!r) + return -EBUSY; + + edmacc_regs_base = ioremap(r->start, len); + if (!edmacc_regs_base) { + status = -EBUSY; + goto fail1; + } + + num_channels = min_t(unsigned, info->n_channel, EDMA_MAX_DMACH); + num_slots = min_t(unsigned, info->n_slot, EDMA_MAX_PARAMENTRY); + + dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base); + + for (i = 0; i < num_slots; i++) + memcpy_toio(edmacc_regs_base + PARM_OFFSET(i), + &dummy_paramset, PARM_SIZE); + + noevent = info->noevent; + if (noevent) { + while (*noevent != -1) + set_bit(*noevent++, edma_noevent); + } + + irq = platform_get_irq(pdev, 0); + status = request_irq(irq, dma_irq_handler, 0, "edma", &pdev->dev); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", + irq, status); + goto fail; + } + + err_irq = platform_get_irq(pdev, 1); + status = request_irq(err_irq, dma_ccerr_handler, 0, + "edma_error", &pdev->dev); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", + err_irq, status); + goto fail; + } + + if (tc_errs_handled) { + status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0, + "edma_tc0", &pdev->dev); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", + IRQ_TCERRINT0, status); + return status; + } + status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0, + "edma_tc1", &pdev->dev); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d --> %d\n", + IRQ_TCERRINT, status); + return status; + } + } + + /* Everything lives on transfer controller 1 until otherwise specified. + * This way, long transfers on the low priority queue + * started by the codec engine will not cause audio defects. + */ + for (i = 0; i < num_channels; i++) + map_dmach_queue(i, EVENTQ_1); + + /* Event queue to TC mapping */ + for (i = 0; queue_tc_mapping[i][0] != -1; i++) + map_queue_tc(queue_tc_mapping[i][0], queue_tc_mapping[i][1]); + + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + assign_priority_to_queue(queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); + + for (i = 0; i < info->n_region; i++) { + edma_write_array2(EDMA_DRAE, i, 0, 0x0); + edma_write_array2(EDMA_DRAE, i, 1, 0x0); + edma_write_array(EDMA_QRAE, i, 0x0); + } + + return 0; + +fail: + if (err_irq) + free_irq(err_irq, NULL); + if (irq) + free_irq(irq, NULL); + iounmap(edmacc_regs_base); +fail1: + release_mem_region(r->start, len); + return status; +} + + +static struct platform_driver edma_driver = { + .driver.name = "edma", +}; + +static int __init edma_init(void) +{ + return platform_driver_probe(&edma_driver, edma_probe); +} +arch_initcall(edma_init); + diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index b49e9d0..1aba41c 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -20,6 +20,7 @@ #include <linux/irq.h> #include <linux/bitops.h> +#include <mach/cputype.h> #include <mach/irqs.h> #include <mach/hardware.h> #include <mach/gpio.h> @@ -36,9 +37,10 @@ struct davinci_gpio { static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; +static unsigned __initdata ngpio; /* create a non-inlined version */ -static struct gpio_controller *__iomem __init gpio2controller(unsigned gpio) +static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio) { return __gpio_to_controller(gpio); } @@ -114,9 +116,30 @@ static int __init davinci_gpio_setup(void) { int i, base; - for (i = 0, base = 0; - i < ARRAY_SIZE(chips); - i++, base += 32) { + /* The gpio banks conceptually expose a segmented bitmap, + * and "ngpio" is one more than the largest zero-based + * bit index that's valid. + */ + if (cpu_is_davinci_dm355()) { /* or dm335() */ + ngpio = 104; + } else if (cpu_is_davinci_dm644x()) { /* or dm337() */ + ngpio = 71; + } else if (cpu_is_davinci_dm646x()) { + /* NOTE: each bank has several "reserved" bits, + * unusable as GPIOs. Only 33 of the GPIO numbers + * are usable, and we're not rejecting the others. + */ + ngpio = 43; + } else { + /* if cpu_is_davinci_dm643x() ngpio = 111 */ + pr_err("GPIO setup: how many GPIOs?\n"); + return -EINVAL; + } + + if (WARN_ON(DAVINCI_N_GPIO < ngpio)) + ngpio = DAVINCI_N_GPIO; + + for (i = 0, base = 0; base < ngpio; i++, base += 32) { chips[i].chip.label = "DaVinci"; chips[i].chip.direction_input = davinci_direction_in; @@ -125,7 +148,7 @@ static int __init davinci_gpio_setup(void) chips[i].chip.set = davinci_gpio_set; chips[i].chip.base = base; - chips[i].chip.ngpio = DAVINCI_N_GPIO - base; + chips[i].chip.ngpio = ngpio - base; if (chips[i].chip.ngpio > 32) chips[i].chip.ngpio = 32; @@ -143,11 +166,11 @@ pure_initcall(davinci_gpio_setup); * We expect irqs will normally be set up as input pins, but they can also be * used as output pins ... which is convenient for testing. * - * NOTE: GPIO0..GPIO7 also have direct INTC hookups, which work in addition - * to their GPIOBNK0 irq (but with a bit less overhead). But we don't have - * a good way to hook those up ... + * NOTE: The first few GPIOs also have direct INTC hookups in addition + * to their GPIOBNK0 irq, with a bit less overhead but less flexibility + * on triggering (e.g. no edge options). We don't try to use those. * - * All those INTC hookups (GPIO0..GPIO7 plus five IRQ banks) can also + * All those INTC hookups (direct, plus several IRQ banks) can also * serve as EDMA event triggers. */ @@ -235,29 +258,42 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) } /* - * NOTE: for suspend/resume, probably best to make a sysdev (and class) - * with its suspend/resume calls hooking into the results of the set_wake() + * NOTE: for suspend/resume, probably best to make a platform_device with + * suspend_late/resume_resume calls hooking into results of the set_wake() * calls ... so if no gpios are wakeup events the clock can be disabled, * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 - * can be set appropriately for GPIOV33 pins. + * (dm6446) can be set appropriately for GPIOV33 pins. */ static int __init davinci_gpio_irq_setup(void) { unsigned gpio, irq, bank; + unsigned bank_irq; struct clk *clk; + u32 binten = 0; + + if (cpu_is_davinci_dm355()) { /* or dm335() */ + bank_irq = IRQ_DM355_GPIOBNK0; + } else if (cpu_is_davinci_dm644x()) { + bank_irq = IRQ_GPIOBNK0; + } else if (cpu_is_davinci_dm646x()) { + bank_irq = IRQ_DM646X_GPIOBNK0; + } else { + printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); + return -EINVAL; + } clk = clk_get(NULL, "gpio"); if (IS_ERR(clk)) { printk(KERN_ERR "Error %ld getting gpio clock?\n", PTR_ERR(clk)); - return 0; + return PTR_ERR(clk); } - clk_enable(clk); - for (gpio = 0, irq = gpio_to_irq(0), bank = IRQ_GPIOBNK0; - gpio < DAVINCI_N_GPIO; bank++) { + for (gpio = 0, irq = gpio_to_irq(0), bank = 0; + gpio < ngpio; + bank++, bank_irq++) { struct gpio_controller *__iomem g = gpio2controller(gpio); unsigned i; @@ -265,28 +301,28 @@ static int __init davinci_gpio_irq_setup(void) __raw_writel(~0, &g->clr_rising); /* set up all irqs in this bank */ - set_irq_chained_handler(bank, gpio_irq_handler); - set_irq_chip_data(bank, g); - set_irq_data(bank, (void *)irq); + set_irq_chained_handler(bank_irq, gpio_irq_handler); + set_irq_chip_data(bank_irq, g); + set_irq_data(bank_irq, (void *)irq); - for (i = 0; i < 16 && gpio < DAVINCI_N_GPIO; - i++, irq++, gpio++) { + for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { set_irq_chip(irq, &gpio_irqchip); set_irq_chip_data(irq, g); set_irq_handler(irq, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); } + + binten |= BIT(bank); } /* BINTEN -- per-bank interrupt enable. genirq would also let these * bits be set/cleared dynamically. */ - __raw_writel(0x1f, (void *__iomem) + __raw_writel(binten, (void *__iomem) IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08)); printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); return 0; } - arch_initcall(davinci_gpio_irq_setup); diff --git a/arch/arm/mach-davinci/id.c b/arch/arm/mach-davinci/id.c index bf067d6..018b994 100644 --- a/arch/arm/mach-davinci/id.c +++ b/arch/arm/mach-davinci/id.c @@ -15,7 +15,9 @@ #include <linux/init.h> #include <linux/io.h> -#define JTAG_ID_BASE 0x01c40028 +#define JTAG_ID_BASE IO_ADDRESS(0x01c40028) + +static unsigned int davinci_revision; struct davinci_id { u8 variant; /* JTAG ID bits 31:28 */ @@ -33,6 +35,20 @@ static struct davinci_id davinci_ids[] __initdata = { .manufacturer = 0x017, .type = 0x64460000, }, + { + /* DM646X */ + .part_no = 0xb770, + .variant = 0x0, + .manufacturer = 0x017, + .type = 0x64670000, + }, + { + /* DM355 */ + .part_no = 0xb73b, + .variant = 0x0, + .manufacturer = 0x00f, + .type = 0x03550000, + }, }; /* @@ -42,7 +58,7 @@ static u16 __init davinci_get_part_no(void) { u32 dev_id, part_no; - dev_id = davinci_readl(JTAG_ID_BASE); + dev_id = __raw_readl(JTAG_ID_BASE); part_no = ((dev_id >> 12) & 0xffff); @@ -56,13 +72,19 @@ static u8 __init davinci_get_variant(void) { u32 variant; - variant = davinci_readl(JTAG_ID_BASE); + variant = __raw_readl(JTAG_ID_BASE); variant = (variant >> 28) & 0xf; return variant; } +unsigned int davinci_rev(void) +{ + return davinci_revision >> 16; +} +EXPORT_SYMBOL(davinci_rev); + void __init davinci_check_revision(void) { int i; @@ -75,7 +97,7 @@ void __init davinci_check_revision(void) /* First check only the major version in a safe way */ for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { if (part_no == (davinci_ids[i].part_no)) { - system_rev = davinci_ids[i].type; + davinci_revision = davinci_ids[i].type; break; } } @@ -84,10 +106,11 @@ void __init davinci_check_revision(void) for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { if (part_no == davinci_ids[i].part_no && variant == davinci_ids[i].variant) { - system_rev = davinci_ids[i].type; + davinci_revision = davinci_ids[i].type; break; } } - printk("DaVinci DM%04x variant 0x%x\n", system_rev >> 16, variant); + printk(KERN_INFO "DaVinci DM%04x variant 0x%x\n", + davinci_rev(), variant); } diff --git a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h new file mode 100644 index 0000000..3216f21 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h @@ -0,0 +1,20 @@ +/* + * DaVinci DM6446 EVM board specific headers + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or ifndef. + */ + +#ifndef _MACH_DAVINCI_DM6446EVM_H +#define _MACH_DAVINCI_DM6446EVM_H + +#include <linux/types.h> + +int dm6446evm_eeprom_read(char *buf, off_t off, size_t count); +int dm6446evm_eeprom_write(char *buf, off_t off, size_t count); + +#endif diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h new file mode 100644 index 0000000..730c49d --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/clkdev.h @@ -0,0 +1,13 @@ +#ifndef __MACH_CLKDEV_H +#define __MACH_CLKDEV_H + +static inline int __clk_get(struct clk *clk) +{ + return 1; +} + +static inline void __clk_put(struct clk *clk) +{ +} + +#endif diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h index 38bdd49..a3b0402 100644 --- a/arch/arm/mach-davinci/include/mach/clock.h +++ b/arch/arm/mach-davinci/include/mach/clock.h @@ -17,6 +17,5 @@ struct clk; extern int clk_register(struct clk *clk); extern void clk_unregister(struct clk *clk); -extern int davinci_clk_init(void); #endif diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index 4b522e5..1917709 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -16,6 +16,12 @@ struct sys_timer; extern struct sys_timer davinci_timer; +extern void davinci_irq_init(void); +extern void davinci_map_common_io(void); + +/* parameters describe VBUS sourcing for host mode */ +extern void setup_usb(unsigned mA, unsigned potpgt_msec); + /* parameters describe VBUS sourcing for host mode */ extern void setup_usb(unsigned mA, unsigned potpgt_msec); diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h new file mode 100644 index 0000000..27cfb1b --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -0,0 +1,49 @@ +/* + * DaVinci CPU type detection + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * Defines the cpu_is_*() macros for runtime detection of DaVinci + * device type. In addtion, if support for a given device is not + * compiled in to the kernel, the macros return 0 so that + * resulting code can be optimized out. + * + * 2009 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef _ASM_ARCH_CPU_H +#define _ASM_ARCH_CPU_H + +extern unsigned int davinci_rev(void); + +#define IS_DAVINCI_CPU(type, id) \ +static inline int is_davinci_dm ##type(void) \ +{ \ + return (davinci_rev() == (id)) ? 1 : 0; \ +} + +IS_DAVINCI_CPU(644x, 0x6446) +IS_DAVINCI_CPU(646x, 0x6467) +IS_DAVINCI_CPU(355, 0x355) + +#ifdef CONFIG_ARCH_DAVINCI_DM644x +#define cpu_is_davinci_dm644x() is_davinci_dm644x() +#else +#define cpu_is_davinci_dm644x() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DM646x +#define cpu_is_davinci_dm646x() is_davinci_dm646x() +#else +#define cpu_is_davinci_dm646x() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DM355 +#define cpu_is_davinci_dm355() is_davinci_dm355() +#else +#define cpu_is_davinci_dm355() 0 +#endif + +#endif diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h new file mode 100644 index 0000000..3dcb9f4 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dm644x.h @@ -0,0 +1,37 @@ +/* + * This file contains the processor specific definitions + * of the TI DM644x. + * + * Copyright (C) 2008 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef __ASM_ARCH_DM644X_H +#define __ASM_ARCH_DM644X_H + +#include <linux/platform_device.h> +#include <mach/hardware.h> + +#define DM644X_EMAC_BASE (0x01C80000) +#define DM644X_EMAC_CNTRL_OFFSET (0x0000) +#define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000) +#define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000) +#define DM644X_EMAC_MDIO_OFFSET (0x4000) +#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) + +void __init dm644x_init(void); + +#endif /* __ASM_ARCH_DM644X_H */ diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h new file mode 100644 index 0000000..f6fc539 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -0,0 +1,228 @@ +/* + * TI DAVINCI dma definitions + * + * Copyright (C) 2006-2009 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +/* + * This EDMA3 programming framework exposes two basic kinds of resource: + * + * Channel Triggers transfers, usually from a hardware event but + * also manually or by "chaining" from DMA completions. + * Each channel is coupled to a Parameter RAM (PaRAM) slot. + * + * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM + * "set"), source and destination addresses, a link to a + * next PaRAM slot (if any), options for the transfer, and + * instructions for updating those addresses. There are + * more than twice as many slots as event channels. + * + * Each PaRAM set describes a sequence of transfers, either for one large + * buffer or for several discontiguous smaller buffers. An EDMA transfer + * is driven only from a channel, which performs the transfers specified + * in its PaRAM slot until there are no more transfers. When that last + * transfer completes, the "link" field may be used to reload the channel's + * PaRAM slot with a new transfer descriptor. + * + * The EDMA Channel Controller (CC) maps requests from channels into physical + * Transfer Controller (TC) requests when the channel triggers (by hardware + * or software events, or by chaining). The two physical DMA channels provided + * by the TCs are thus shared by many logical channels. + * + * DaVinci hardware also has a "QDMA" mechanism which is not currently + * supported through this interface. (DSP firmware uses it though.) + */ + +#ifndef EDMA_H_ +#define EDMA_H_ + +/* PaRAM slots are laid out like this */ +struct edmacc_param { + unsigned int opt; + unsigned int src; + unsigned int a_b_cnt; + unsigned int dst; + unsigned int src_dst_bidx; + unsigned int link_bcntrld; + unsigned int src_dst_cidx; + unsigned int ccnt; +}; + +#define CCINT0_INTERRUPT 16 +#define CCERRINT_INTERRUPT 17 +#define TCERRINT0_INTERRUPT 18 +#define TCERRINT1_INTERRUPT 19 + +/* fields in edmacc_param.opt */ +#define SAM BIT(0) +#define DAM BIT(1) +#define SYNCDIM BIT(2) +#define STATIC BIT(3) +#define EDMA_FWID (0x07 << 8) +#define TCCMODE BIT(11) +#define EDMA_TCC(t) ((t) << 12) +#define TCINTEN BIT(20) +#define ITCINTEN BIT(21) +#define TCCHEN BIT(22) +#define ITCCHEN BIT(23) + +#define TRWORD (0x7<<2) +#define PAENTRY (0x1ff<<5) + +/* Drivers should avoid using these symbolic names for dm644x + * channels, and use platform_device IORESOURCE_DMA resources + * instead. (Other DaVinci chips have different peripherals + * and thus have different DMA channel mappings.) + */ +#define DAVINCI_DMA_MCBSP_TX 2 +#define DAVINCI_DMA_MCBSP_RX 3 +#define DAVINCI_DMA_VPSS_HIST 4 +#define DAVINCI_DMA_VPSS_H3A 5 +#define DAVINCI_DMA_VPSS_PRVU 6 +#define DAVINCI_DMA_VPSS_RSZ 7 +#define DAVINCI_DMA_IMCOP_IMXINT 8 +#define DAVINCI_DMA_IMCOP_VLCDINT 9 +#define DAVINCI_DMA_IMCO_PASQINT 10 +#define DAVINCI_DMA_IMCOP_DSQINT 11 +#define DAVINCI_DMA_SPI_SPIX 16 +#define DAVINCI_DMA_SPI_SPIR 17 +#define DAVINCI_DMA_UART0_URXEVT0 18 +#define DAVINCI_DMA_UART0_UTXEVT0 19 +#define DAVINCI_DMA_UART1_URXEVT1 20 +#define DAVINCI_DMA_UART1_UTXEVT1 21 +#define DAVINCI_DMA_UART2_URXEVT2 22 +#define DAVINCI_DMA_UART2_UTXEVT2 23 +#define DAVINCI_DMA_MEMSTK_MSEVT 24 +#define DAVINCI_DMA_MMCRXEVT 26 +#define DAVINCI_DMA_MMCTXEVT 27 +#define DAVINCI_DMA_I2C_ICREVT 28 +#define DAVINCI_DMA_I2C_ICXEVT 29 +#define DAVINCI_DMA_GPIO_GPINT0 32 +#define DAVINCI_DMA_GPIO_GPINT1 33 +#define DAVINCI_DMA_GPIO_GPINT2 34 +#define DAVINCI_DMA_GPIO_GPINT3 35 +#define DAVINCI_DMA_GPIO_GPINT4 36 +#define DAVINCI_DMA_GPIO_GPINT5 37 +#define DAVINCI_DMA_GPIO_GPINT6 38 +#define DAVINCI_DMA_GPIO_GPINT7 39 +#define DAVINCI_DMA_GPIO_GPBNKINT0 40 +#define DAVINCI_DMA_GPIO_GPBNKINT1 41 +#define DAVINCI_DMA_GPIO_GPBNKINT2 42 +#define DAVINCI_DMA_GPIO_GPBNKINT3 43 +#define DAVINCI_DMA_GPIO_GPBNKINT4 44 +#define DAVINCI_DMA_TIMER0_TINT0 48 +#define DAVINCI_DMA_TIMER1_TINT1 49 +#define DAVINCI_DMA_TIMER2_TINT2 50 +#define DAVINCI_DMA_TIMER3_TINT3 51 +#define DAVINCI_DMA_PWM0 52 +#define DAVINCI_DMA_PWM1 53 +#define DAVINCI_DMA_PWM2 54 + +/*ch_status paramater of callback function possible values*/ +#define DMA_COMPLETE 1 +#define DMA_CC_ERROR 2 +#define DMA_TC1_ERROR 3 +#define DMA_TC2_ERROR 4 + +enum address_mode { + INCR = 0, + FIFO = 1 +}; + +enum fifo_width { + W8BIT = 0, + W16BIT = 1, + W32BIT = 2, + W64BIT = 3, + W128BIT = 4, + W256BIT = 5 +}; + +enum dma_event_q { + EVENTQ_0 = 0, + EVENTQ_1 = 1, + EVENTQ_DEFAULT = -1 +}; + +enum sync_dimension { + ASYNC = 0, + ABSYNC = 1 +}; + +#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ +#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ + +/* alloc/free DMA channels and their dedicated parameter RAM slots */ +int edma_alloc_channel(int channel, + void (*callback)(unsigned channel, u16 ch_status, void *data), + void *data, enum dma_event_q); +void edma_free_channel(unsigned channel); + +/* alloc/free parameter RAM slots */ +int edma_alloc_slot(int slot); +void edma_free_slot(unsigned slot); + +/* calls that operate on part of a parameter RAM slot */ +void edma_set_src(unsigned slot, dma_addr_t src_port, + enum address_mode mode, enum fifo_width); +void edma_set_dest(unsigned slot, dma_addr_t dest_port, + enum address_mode mode, enum fifo_width); +void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst); +void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx); +void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx); +void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt, + u16 bcnt_rld, enum sync_dimension sync_mode); +void edma_link(unsigned from, unsigned to); +void edma_unlink(unsigned from); + +/* calls that operate on an entire parameter RAM slot */ +void edma_write_slot(unsigned slot, const struct edmacc_param *params); +void edma_read_slot(unsigned slot, struct edmacc_param *params); + +/* channel control operations */ +int edma_start(unsigned channel); +void edma_stop(unsigned channel); +void edma_clean_channel(unsigned channel); +void edma_clear_event(unsigned channel); +void edma_pause(unsigned channel); +void edma_resume(unsigned channel); + +/* UNRELATED TO DMA */ +int davinci_alloc_iram(unsigned size); +void davinci_free_iram(unsigned addr, unsigned size); + +/* platform_data for EDMA driver */ +struct edma_soc_info { + + /* how many dma resources of each type */ + unsigned n_channel; + unsigned n_region; + unsigned n_slot; + unsigned n_tc; + + /* list of channels with no even trigger; terminated by "-1" */ + const s8 *noevent; +}; + +#endif diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index b456f07..efe3281 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -15,9 +15,11 @@ #include <linux/io.h> #include <asm-generic/gpio.h> -#include <mach/hardware.h> + #include <mach/irqs.h> +#define DAVINCI_GPIO_BASE 0x01C67000 + /* * basic gpio routines * @@ -26,23 +28,18 @@ * go through boot loaders. * * the gpio clock will be turned on when gpios are used, and you may also - * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are + * need to pay attention to PINMUX registers to be sure those pins are * used as gpios, not with other peripherals. * * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, - * and maybe for later updates, code should write GPIO(N) or: - * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53) - * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70) - * - * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc - * for now, that's != GPIO(N) + * and maybe for later updates, code may write GPIO(N). These may be + * all 1.8V signals, all 3.3V ones, or a mix of the two. A given chip + * may not support all the GPIOs in that range. * * GPIOs can also be on external chips, numbered after the ones built-in * to the DaVinci chip. For now, they won't be usable as IRQ sources. */ -#define GPIO(X) (X) /* 0 <= X <= 70 */ -#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */ -#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */ +#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */ struct gpio_controller { u32 dir; @@ -71,12 +68,14 @@ __gpio_to_controller(unsigned gpio) { void *__iomem ptr; - if (gpio < 32) + if (gpio < 32 * 1) ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); - else if (gpio < 64) + else if (gpio < 32 * 2) ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); - else if (gpio < DAVINCI_N_GPIO) + else if (gpio < 32 * 3) ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); + else if (gpio < 32 * 4) + ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x88); else ptr = NULL; return ptr; diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index a2e8969..48c7793 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h @@ -1,9 +1,9 @@ /* - * Common hardware definitions + * Hardware definitions common to all DaVinci family processors * - * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * Author: Kevin Hilman, Deep Root Systems, LLC * - * 2007 (c) MontaVista Software, Inc. This file is licensed under + * 2007 (c) Deep Root Systems, LLC. This file is licensed under * the terms of the GNU General Public License version 2. This program * is licensed "as is" without any warranty of any kind, whether express * or implied. @@ -12,41 +12,16 @@ #define __ASM_ARCH_HARDWARE_H /* - * Base register addresses + * Before you add anything to ths file: + * + * This header is for defines common to ALL DaVinci family chips. + * Anything that is chip specific should go in <chipname>.h, + * and the chip/board init code should then explicitly include + * <chipname>.h */ -#define DAVINCI_DMA_3PCC_BASE (0x01C00000) -#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) -#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) -#define DAVINCI_I2C_BASE (0x01C21000) -#define DAVINCI_PWM0_BASE (0x01C22000) -#define DAVINCI_PWM1_BASE (0x01C22400) -#define DAVINCI_PWM2_BASE (0x01C22800) -#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) -#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) -#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) -#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) -#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) -#define DAVINCI_IEEE1394_BASE (0x01C60000) -#define DAVINCI_USB_OTG_BASE (0x01C64000) -#define DAVINCI_CFC_ATA_BASE (0x01C66000) -#define DAVINCI_SPI_BASE (0x01C66800) -#define DAVINCI_GPIO_BASE (0x01C67000) -#define DAVINCI_UHPI_BASE (0x01C67800) -#define DAVINCI_VPSS_REGS_BASE (0x01C70000) -#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) -#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) -#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) -#define DAVINCI_IMCOP_BASE (0x01CC0000) -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) -#define DAVINCI_VLYNQ_BASE (0x01E01000) -#define DAVINCI_MCBSP_BASE (0x01E02000) -#define DAVINCI_MMC_SD_BASE (0x01E10000) -#define DAVINCI_MS_BASE (0x01E20000) -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) -#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) +#define DAVINCI_SYSTEM_MODULE_BASE 0x01C40000 + +/* System control register offsets */ +#define DM64XX_VDD3P3V_PWDN 0x48 #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h index a48795f..2479785 100644 --- a/arch/arm/mach-davinci/include/mach/io.h +++ b/arch/arm/mach-davinci/include/mach/io.h @@ -40,22 +40,12 @@ #else #define IOMEM(x) ((void __force __iomem *)(x)) -/* - * Functions to access the DaVinci IO region - * - * NOTE: - Use davinci_read/write[bwl] for physical register addresses - * - Use __raw_read/write[bwl]() for virtual register addresses - * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses - * - DO NOT use hardcoded virtual addresses to allow changing the - * IO address space again if needed - */ -#define davinci_readb(a) __raw_readb(IO_ADDRESS(a)) -#define davinci_readw(a) __raw_readw(IO_ADDRESS(a)) -#define davinci_readl(a) __raw_readl(IO_ADDRESS(a)) +#define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t) +#define __arch_iounmap(v) davinci_iounmap(v) -#define davinci_writeb(v, a) __raw_writeb(v, IO_ADDRESS(a)) -#define davinci_writew(v, a) __raw_writew(v, IO_ADDRESS(a)) -#define davinci_writel(v, a) __raw_writel(v, IO_ADDRESS(a)) +void __iomem *davinci_ioremap(unsigned long phys, size_t size, + unsigned int type); +void davinci_iounmap(volatile void __iomem *addr); #endif /* __ASSEMBLER__ */ #endif /* __ASM_ARCH_IO_H */ diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index f4c5ca6..1806607 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -96,10 +96,111 @@ #define IRQ_EMUINT 63 #define DAVINCI_N_AINTC_IRQ 64 -#define DAVINCI_N_GPIO 71 +#define DAVINCI_N_GPIO 104 #define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 +/* DaVinci DM6467-specific Interrupts */ +#define IRQ_DM646X_VP_VERTINT0 0 +#define IRQ_DM646X_VP_VERTINT1 1 +#define IRQ_DM646X_VP_VERTINT2 2 +#define IRQ_DM646X_VP_VERTINT3 3 +#define IRQ_DM646X_VP_ERRINT 4 +#define IRQ_DM646X_RESERVED_1 5 +#define IRQ_DM646X_RESERVED_2 6 +#define IRQ_DM646X_WDINT 7 +#define IRQ_DM646X_CRGENINT0 8 +#define IRQ_DM646X_CRGENINT1 9 +#define IRQ_DM646X_TSIFINT0 10 +#define IRQ_DM646X_TSIFINT1 11 +#define IRQ_DM646X_VDCEINT 12 +#define IRQ_DM646X_USBINT 13 +#define IRQ_DM646X_USBDMAINT 14 +#define IRQ_DM646X_PCIINT 15 +#define IRQ_DM646X_TCERRINT2 20 +#define IRQ_DM646X_TCERRINT3 21 +#define IRQ_DM646X_IDE 22 +#define IRQ_DM646X_HPIINT 23 +#define IRQ_DM646X_EMACRXTHINT 24 +#define IRQ_DM646X_EMACRXINT 25 +#define IRQ_DM646X_EMACTXINT 26 +#define IRQ_DM646X_EMACMISCINT 27 +#define IRQ_DM646X_MCASP0TXINT 28 +#define IRQ_DM646X_MCASP0RXINT 29 +#define IRQ_DM646X_RESERVED_3 31 +#define IRQ_DM646X_MCASP1TXINT 32 +#define IRQ_DM646X_VLQINT 38 +#define IRQ_DM646X_UARTINT2 42 +#define IRQ_DM646X_SPINT0 43 +#define IRQ_DM646X_SPINT1 44 +#define IRQ_DM646X_DSP2ARMINT 45 +#define IRQ_DM646X_RESERVED_4 46 +#define IRQ_DM646X_PSCINT 47 +#define IRQ_DM646X_GPIO0 48 +#define IRQ_DM646X_GPIO1 49 +#define IRQ_DM646X_GPIO2 50 +#define IRQ_DM646X_GPIO3 51 +#define IRQ_DM646X_GPIO4 52 +#define IRQ_DM646X_GPIO5 53 +#define IRQ_DM646X_GPIO6 54 +#define IRQ_DM646X_GPIO7 55 +#define IRQ_DM646X_GPIOBNK0 56 +#define IRQ_DM646X_GPIOBNK1 57 +#define IRQ_DM646X_GPIOBNK2 58 +#define IRQ_DM646X_DDRINT 59 +#define IRQ_DM646X_AEMIFINT 60 + +/* DaVinci DM355-specific Interrupts */ +#define IRQ_DM355_CCDC_VDINT0 0 +#define IRQ_DM355_CCDC_VDINT1 1 +#define IRQ_DM355_CCDC_VDINT2 2 +#define IRQ_DM355_IPIPE_HST 3 +#define IRQ_DM355_H3AINT 4 +#define IRQ_DM355_IPIPE_SDR 5 +#define IRQ_DM355_IPIPEIFINT 6 +#define IRQ_DM355_OSDINT 7 +#define IRQ_DM355_VENCINT 8 +#define IRQ_DM355_IMCOPINT 11 +#define IRQ_DM355_RTOINT 13 +#define IRQ_DM355_TINT4 13 +#define IRQ_DM355_TINT2_TINT12 13 +#define IRQ_DM355_UARTINT2 14 +#define IRQ_DM355_TINT5 14 +#define IRQ_DM355_TINT2_TINT34 14 +#define IRQ_DM355_TINT6 15 +#define IRQ_DM355_TINT3_TINT12 15 +#define IRQ_DM355_SPINT1_0 17 +#define IRQ_DM355_SPINT1_1 18 +#define IRQ_DM355_SPINT2_0 19 +#define IRQ_DM355_SPINT2_1 21 +#define IRQ_DM355_TINT7 22 +#define IRQ_DM355_TINT3_TINT34 22 +#define IRQ_DM355_SDIOINT0 23 +#define IRQ_DM355_MMCINT0 26 +#define IRQ_DM355_MSINT 26 +#define IRQ_DM355_MMCINT1 27 +#define IRQ_DM355_PWMINT3 28 +#define IRQ_DM355_SDIOINT1 31 +#define IRQ_DM355_SPINT0_0 42 +#define IRQ_DM355_SPINT0_1 43 +#define IRQ_DM355_GPIO0 44 +#define IRQ_DM355_GPIO1 45 +#define IRQ_DM355_GPIO2 46 +#define IRQ_DM355_GPIO3 47 +#define IRQ_DM355_GPIO4 48 +#define IRQ_DM355_GPIO5 49 +#define IRQ_DM355_GPIO6 50 +#define IRQ_DM355_GPIO7 51 +#define IRQ_DM355_GPIO8 52 +#define IRQ_DM355_GPIO9 53 +#define IRQ_DM355_GPIOBNK0 54 +#define IRQ_DM355_GPIOBNK1 55 +#define IRQ_DM355_GPIOBNK2 56 +#define IRQ_DM355_GPIOBNK3 57 +#define IRQ_DM355_GPIOBNK4 58 +#define IRQ_DM355_GPIOBNK5 59 +#define IRQ_DM355_GPIOBNK6 60 + #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index c24b678..bae22cb 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -1,55 +1,183 @@ /* - * DaVinci pin multiplexing defines + * Table of the DAVINCI register configurations for the PINMUX combinations * * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> * + * Based on linux/include/asm-arm/arch-omap/mux.h: + * Copyright (C) 2003 - 2005 Nokia Corporation + * + * Written by Tony Lindgren + * * 2007 (c) MontaVista Software, Inc. This file is licensed under * the terms of the GNU General Public License version 2. This program * is licensed "as is" without any warranty of any kind, whether express * or implied. + * + * Copyright (C) 2008 Texas Instruments. */ -#ifndef __ASM_ARCH_MUX_H -#define __ASM_ARCH_MUX_H - -#define DAVINCI_MUX_AEAW0 0 -#define DAVINCI_MUX_AEAW1 1 -#define DAVINCI_MUX_AEAW2 2 -#define DAVINCI_MUX_AEAW3 3 -#define DAVINCI_MUX_AEAW4 4 -#define DAVINCI_MUX_AECS4 10 -#define DAVINCI_MUX_AECS5 11 -#define DAVINCI_MUX_VLYNQWD0 12 -#define DAVINCI_MUX_VLYNQWD1 13 -#define DAVINCI_MUX_VLSCREN 14 -#define DAVINCI_MUX_VLYNQEN 15 -#define DAVINCI_MUX_HDIREN 16 -#define DAVINCI_MUX_ATAEN 17 -#define DAVINCI_MUX_RGB666 22 -#define DAVINCI_MUX_RGB888 23 -#define DAVINCI_MUX_LOEEN 24 -#define DAVINCI_MUX_LFLDEN 25 -#define DAVINCI_MUX_CWEN 26 -#define DAVINCI_MUX_CFLDEN 27 -#define DAVINCI_MUX_HPIEN 29 -#define DAVINCI_MUX_1394EN 30 -#define DAVINCI_MUX_EMACEN 31 - -#define DAVINCI_MUX_LEVEL2 32 -#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) -#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) -#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) -#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) -#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) -#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) -#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) -#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) -#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) -#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) -#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) -#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) -#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) -#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) - -extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); - -#endif /* __ASM_ARCH_MUX_H */ + +#ifndef __INC_MACH_MUX_H +#define __INC_MACH_MUX_H + +/* System module registers */ +#define PINMUX0 0x00 +#define PINMUX1 0x04 +/* dm355 only */ +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 +#define INTMUX 0x18 +#define EVTMUX 0x1c + +struct mux_config { + const char *name; + const char *mux_reg_name; + const unsigned char mux_reg; + const unsigned char mask_offset; + const unsigned char mask; + const unsigned char mode; + bool debug; +}; + +enum davinci_dm644x_index { + /* ATA and HDDIR functions */ + DM644X_HDIREN, + DM644X_ATAEN, + DM644X_ATAEN_DISABLE, + + /* HPI functions */ + DM644X_HPIEN_DISABLE, + + /* AEAW functions */ + DM644X_AEAW, + + /* Memory Stick */ + DM644X_MSTK, + + /* I2C */ + DM644X_I2C, + + /* ASP function */ + DM644X_MCBSP, + + /* UART1 */ + DM644X_UART1, + + /* UART2 */ + DM644X_UART2, + + /* PWM0 */ + DM644X_PWM0, + + /* PWM1 */ + DM644X_PWM1, + + /* PWM2 */ + DM644X_PWM2, + + /* VLYNQ function */ + DM644X_VLYNQEN, + DM644X_VLSCREN, + DM644X_VLYNQWD, + + /* EMAC and MDIO function */ + DM644X_EMACEN, + + /* GPIO3V[0:16] pins */ + DM644X_GPIO3V, + + /* GPIO pins */ + DM644X_GPIO0, + DM644X_GPIO3, + DM644X_GPIO43_44, + DM644X_GPIO46_47, + + /* VPBE */ + DM644X_RGB666, + + /* LCD */ + DM644X_LOEEN, + DM644X_LFLDEN, +}; + +enum davinci_dm646x_index { + /* ATA function */ + DM646X_ATAEN, + + /* AUDIO Clock */ + DM646X_AUDCK1, + DM646X_AUDCK0, + + /* CRGEN Control */ + DM646X_CRGMUX, + + /* VPIF Control */ + DM646X_STSOMUX_DISABLE, + DM646X_STSIMUX_DISABLE, + DM646X_PTSOMUX_DISABLE, + DM646X_PTSIMUX_DISABLE, + + /* TSIF Control */ + DM646X_STSOMUX, + DM646X_STSIMUX, + DM646X_PTSOMUX_PARALLEL, + DM646X_PTSIMUX_PARALLEL, + DM646X_PTSOMUX_SERIAL, + DM646X_PTSIMUX_SERIAL, +}; + +enum davinci_dm355_index { + /* MMC/SD 0 */ + DM355_MMCSD0, + + /* MMC/SD 1 */ + DM355_SD1_CLK, + DM355_SD1_CMD, + DM355_SD1_DATA3, + DM355_SD1_DATA2, + DM355_SD1_DATA1, + DM355_SD1_DATA0, + + /* I2C */ + DM355_I2C_SDA, + DM355_I2C_SCL, + + /* ASP0 function */ + DM355_MCBSP0_BDX, + DM355_MCBSP0_X, + DM355_MCBSP0_BFSX, + DM355_MCBSP0_BDR, + DM355_MCBSP0_R, + DM355_MCBSP0_BFSR, + + /* SPI0 */ + DM355_SPI0_SDI, + DM355_SPI0_SDENA0, + DM355_SPI0_SDENA1, + + /* IRQ muxing */ + DM355_INT_EDMA_CC, + DM355_INT_EDMA_TC0_ERR, + DM355_INT_EDMA_TC1_ERR, + + /* EDMA event muxing */ + DM355_EVT8_ASP1_TX, + DM355_EVT9_ASP1_RX, + DM355_EVT26_MMC0_RX, +}; + +#ifdef CONFIG_DAVINCI_MUX +/* setup pin muxing */ +extern void davinci_mux_init(void); +extern int davinci_mux_register(const struct mux_config *pins, + unsigned long size); +extern int davinci_cfg_reg(unsigned long reg_cfg); +#else +/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ +static inline void davinci_mux_init(void) {} +static inline int davinci_mux_register(const struct mux_config *pins, + unsigned long size) { return 0; } +static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } +#endif + +#endif /* __INC_MACH_MUX_H */ diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 4977aa0..55a90d4 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -38,8 +38,6 @@ #define DAVINCI_LPSC_TPTC1 4 #define DAVINCI_LPSC_EMAC 5 #define DAVINCI_LPSC_EMAC_WRAPPER 6 -#define DAVINCI_LPSC_MDIO 7 -#define DAVINCI_LPSC_IEEE1394 8 #define DAVINCI_LPSC_USB 9 #define DAVINCI_LPSC_ATA 10 #define DAVINCI_LPSC_VLYNQ 11 @@ -47,7 +45,6 @@ #define DAVINCI_LPSC_DDR_EMIF 13 #define DAVINCI_LPSC_AEMIF 14 #define DAVINCI_LPSC_MMC_SD 15 -#define DAVINCI_LPSC_MEMSTICK 16 #define DAVINCI_LPSC_McBSP 17 #define DAVINCI_LPSC_I2C 18 #define DAVINCI_LPSC_UART0 19 @@ -73,4 +70,54 @@ #define DAVINCI_LPSC_GEM 39 #define DAVINCI_LPSC_IMCOP 40 +#define DM355_LPSC_TIMER3 5 +#define DM355_LPSC_SPI1 6 +#define DM355_LPSC_MMC_SD1 7 +#define DM355_LPSC_McBSP1 8 +#define DM355_LPSC_PWM3 10 +#define DM355_LPSC_SPI2 11 +#define DM355_LPSC_RTO 12 +#define DM355_LPSC_VPSS_DAC 41 + +/* + * LPSC Assignments + */ +#define DM646X_LPSC_ARM 0 +#define DM646X_LPSC_C64X_CPU 1 +#define DM646X_LPSC_HDVICP0 2 +#define DM646X_LPSC_HDVICP1 3 +#define DM646X_LPSC_TPCC 4 +#define DM646X_LPSC_TPTC0 5 +#define DM646X_LPSC_TPTC1 6 +#define DM646X_LPSC_TPTC2 7 +#define DM646X_LPSC_TPTC3 8 +#define DM646X_LPSC_PCI 13 +#define DM646X_LPSC_EMAC 14 +#define DM646X_LPSC_VDCE 15 +#define DM646X_LPSC_VPSSMSTR 16 +#define DM646X_LPSC_VPSSSLV 17 +#define DM646X_LPSC_TSIF0 18 +#define DM646X_LPSC_TSIF1 19 +#define DM646X_LPSC_DDR_EMIF 20 +#define DM646X_LPSC_AEMIF 21 +#define DM646X_LPSC_McASP0 22 +#define DM646X_LPSC_McASP1 23 +#define DM646X_LPSC_CRGEN0 24 +#define DM646X_LPSC_CRGEN1 25 +#define DM646X_LPSC_UART0 26 +#define DM646X_LPSC_UART1 27 +#define DM646X_LPSC_UART2 28 +#define DM646X_LPSC_PWM0 29 +#define DM646X_LPSC_PWM1 30 +#define DM646X_LPSC_I2C 31 +#define DM646X_LPSC_SPI 32 +#define DM646X_LPSC_GPIO 33 +#define DM646X_LPSC_TIMER0 34 +#define DM646X_LPSC_TIMER1 35 +#define DM646X_LPSC_ARM_INTC 45 + +extern int davinci_psc_is_clk_active(unsigned int id); +extern void davinci_psc_config(unsigned int domain, unsigned int id, + char enable); + #endif /* __ASM_ARCH_PSC_H */ diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index fb8cb22..632847d 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -13,8 +13,23 @@ #include <mach/io.h> -#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) -#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) -#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) +#define DAVINCI_MAX_NR_UARTS 3 +#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) +#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) +#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) + +#define DM355_UART2_BASE (IO_PHYS + 0x206000) + +/* DaVinci UART register offsets */ +#define UART_DAVINCI_PWREMU 0x0c +#define UART_DM646X_SCR 0x10 +#define UART_DM646X_SCR_TX_WATERMARK 0x08 + +struct davinci_uart_config { + /* Bit field of UARTs present; bit 0 --> UART1 */ + unsigned int enabled_uarts; +}; + +extern void davinci_serial_init(struct davinci_uart_config *); #endif /* __ASM_ARCH_SERIAL_H */ diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c index 299515f..a548abb 100644 --- a/arch/arm/mach-davinci/io.c +++ b/arch/arm/mach-davinci/io.c @@ -51,7 +51,26 @@ void __init davinci_map_common_io(void) davinci_check_revision(); } -void __init davinci_init_common_hw(void) +#define BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) +#define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst))) + +/* + * Intercept ioremap() requests for addresses in our fixed mapping regions. + */ +void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type) +{ + if (BETWEEN(p, IO_PHYS, IO_SIZE)) + return XLATE(p, IO_PHYS, IO_VIRT); + + return __arm_ioremap(p, size, type); +} +EXPORT_SYMBOL(davinci_ioremap); + +void davinci_iounmap(volatile void __iomem *addr) { - davinci_clk_init(); + unsigned long virt = (unsigned long)addr; + + if (virt >= VMALLOC_START && virt < VMALLOC_END) + __iounmap(addr); } +EXPORT_SYMBOL(davinci_iounmap); diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 38021af..5a324c9 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -25,6 +25,7 @@ #include <linux/io.h> #include <mach/hardware.h> +#include <mach/cputype.h> #include <asm/mach/irq.h> #define IRQ_BIT(irq) ((irq) & 0x1f) @@ -40,14 +41,18 @@ #define IRQ_INTPRI0_REG_OFFSET 0x0030 #define IRQ_INTPRI7_REG_OFFSET 0x004C +const u8 *davinci_def_priorities; + +#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE) + static inline unsigned int davinci_irq_readl(int offset) { - return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); + return __raw_readl(INTC_BASE + offset); } static inline void davinci_irq_writel(unsigned long value, int offset) { - davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); + __raw_writel(value, INTC_BASE + offset); } /* Disable interrupt */ @@ -108,9 +113,8 @@ static struct irq_chip davinci_irq_chip_0 = { .unmask = davinci_unmask_irq, }; - /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ -static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { +static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { [IRQ_VDINT0] = 2, [IRQ_VDINT1] = 6, [IRQ_VDINT2] = 6, @@ -177,11 +181,149 @@ static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { [IRQ_EMUINT] = 7, }; +static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { + [IRQ_DM646X_VP_VERTINT0] = 7, + [IRQ_DM646X_VP_VERTINT1] = 7, + [IRQ_DM646X_VP_VERTINT2] = 7, + [IRQ_DM646X_VP_VERTINT3] = 7, + [IRQ_DM646X_VP_ERRINT] = 7, + [IRQ_DM646X_RESERVED_1] = 7, + [IRQ_DM646X_RESERVED_2] = 7, + [IRQ_DM646X_WDINT] = 7, + [IRQ_DM646X_CRGENINT0] = 7, + [IRQ_DM646X_CRGENINT1] = 7, + [IRQ_DM646X_TSIFINT0] = 7, + [IRQ_DM646X_TSIFINT1] = 7, + [IRQ_DM646X_VDCEINT] = 7, + [IRQ_DM646X_USBINT] = 7, + [IRQ_DM646X_USBDMAINT] = 7, + [IRQ_DM646X_PCIINT] = 7, + [IRQ_CCINT0] = 7, /* dma */ + [IRQ_CCERRINT] = 7, /* dma */ + [IRQ_TCERRINT0] = 7, /* dma */ + [IRQ_TCERRINT] = 7, /* dma */ + [IRQ_DM646X_TCERRINT2] = 7, + [IRQ_DM646X_TCERRINT3] = 7, + [IRQ_DM646X_IDE] = 7, + [IRQ_DM646X_HPIINT] = 7, + [IRQ_DM646X_EMACRXTHINT] = 7, + [IRQ_DM646X_EMACRXINT] = 7, + [IRQ_DM646X_EMACTXINT] = 7, + [IRQ_DM646X_EMACMISCINT] = 7, + [IRQ_DM646X_MCASP0TXINT] = 7, + [IRQ_DM646X_MCASP0RXINT] = 7, + [IRQ_AEMIFINT] = 7, + [IRQ_DM646X_RESERVED_3] = 7, + [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ + [IRQ_TINT0_TINT34] = 7, /* clocksource */ + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ + [IRQ_TINT1_TINT34] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_DM646X_VLQINT] = 7, + [IRQ_I2C] = 7, + [IRQ_UARTINT0] = 7, + [IRQ_UARTINT1] = 7, + [IRQ_DM646X_UARTINT2] = 7, + [IRQ_DM646X_SPINT0] = 7, + [IRQ_DM646X_SPINT1] = 7, + [IRQ_DM646X_DSP2ARMINT] = 7, + [IRQ_DM646X_RESERVED_4] = 7, + [IRQ_DM646X_PSCINT] = 7, + [IRQ_DM646X_GPIO0] = 7, + [IRQ_DM646X_GPIO1] = 7, + [IRQ_DM646X_GPIO2] = 7, + [IRQ_DM646X_GPIO3] = 7, + [IRQ_DM646X_GPIO4] = 7, + [IRQ_DM646X_GPIO5] = 7, + [IRQ_DM646X_GPIO6] = 7, + [IRQ_DM646X_GPIO7] = 7, + [IRQ_DM646X_GPIOBNK0] = 7, + [IRQ_DM646X_GPIOBNK1] = 7, + [IRQ_DM646X_GPIOBNK2] = 7, + [IRQ_DM646X_DDRINT] = 7, + [IRQ_DM646X_AEMIFINT] = 7, + [IRQ_COMMTX] = 7, + [IRQ_COMMRX] = 7, + [IRQ_EMUINT] = 7, +}; + +static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = { + [IRQ_DM355_CCDC_VDINT0] = 2, + [IRQ_DM355_CCDC_VDINT1] = 6, + [IRQ_DM355_CCDC_VDINT2] = 6, + [IRQ_DM355_IPIPE_HST] = 6, + [IRQ_DM355_H3AINT] = 6, + [IRQ_DM355_IPIPE_SDR] = 6, + [IRQ_DM355_IPIPEIFINT] = 6, + [IRQ_DM355_OSDINT] = 7, + [IRQ_DM355_VENCINT] = 6, + [IRQ_ASQINT] = 6, + [IRQ_IMXINT] = 6, + [IRQ_USBINT] = 4, + [IRQ_DM355_RTOINT] = 4, + [IRQ_DM355_UARTINT2] = 7, + [IRQ_DM355_TINT6] = 7, + [IRQ_CCINT0] = 5, /* dma */ + [IRQ_CCERRINT] = 5, /* dma */ + [IRQ_TCERRINT0] = 5, /* dma */ + [IRQ_TCERRINT] = 5, /* dma */ + [IRQ_DM355_SPINT2_1] = 7, + [IRQ_DM355_TINT7] = 4, + [IRQ_DM355_SDIOINT0] = 7, + [IRQ_MBXINT] = 7, + [IRQ_MBRINT] = 7, + [IRQ_MMCINT] = 7, + [IRQ_DM355_MMCINT1] = 7, + [IRQ_DM355_PWMINT3] = 7, + [IRQ_DDRINT] = 7, + [IRQ_AEMIFINT] = 7, + [IRQ_DM355_SDIOINT1] = 4, + [IRQ_TINT0_TINT12] = 2, /* clockevent */ + [IRQ_TINT0_TINT34] = 2, /* clocksource */ + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ + [IRQ_TINT1_TINT34] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_PWMINT2] = 7, + [IRQ_I2C] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_DM355_SPINT0_0] = 3, + [IRQ_DM355_SPINT0_1] = 3, + [IRQ_DM355_GPIO0] = 3, + [IRQ_DM355_GPIO1] = 7, + [IRQ_DM355_GPIO2] = 4, + [IRQ_DM355_GPIO3] = 4, + [IRQ_DM355_GPIO4] = 7, + [IRQ_DM355_GPIO5] = 7, + [IRQ_DM355_GPIO6] = 7, + [IRQ_DM355_GPIO7] = 7, + [IRQ_DM355_GPIO8] = 7, + [IRQ_DM355_GPIO9] = 7, + [IRQ_DM355_GPIOBNK0] = 7, + [IRQ_DM355_GPIOBNK1] = 7, + [IRQ_DM355_GPIOBNK2] = 7, + [IRQ_DM355_GPIOBNK3] = 7, + [IRQ_DM355_GPIOBNK4] = 7, + [IRQ_DM355_GPIOBNK5] = 7, + [IRQ_DM355_GPIOBNK6] = 7, + [IRQ_COMMTX] = 7, + [IRQ_COMMRX] = 7, + [IRQ_EMUINT] = 7, +}; + /* ARM Interrupt Controller Initialization */ void __init davinci_irq_init(void) { unsigned i; - const u8 *priority = default_priorities; + + if (cpu_is_davinci_dm644x()) + davinci_def_priorities = dm644x_default_priorities; + else if (cpu_is_davinci_dm646x()) + davinci_def_priorities = dm646x_default_priorities; + else if (cpu_is_davinci_dm355()) + davinci_def_priorities = dm355_default_priorities; /* Clear all interrupt requests */ davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); @@ -209,8 +351,8 @@ void __init davinci_irq_init(void) unsigned j; u32 pri; - for (j = 0, pri = 0; j < 32; j += 4, priority++) - pri |= (*priority & 0x07) << j; + for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++) + pri |= (*davinci_def_priorities & 0x07) << j; davinci_irq_writel(pri, i); } diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c index 8ff9d8a..bbba0b2 100644 --- a/arch/arm/mach-davinci/mux.c +++ b/arch/arm/mach-davinci/mux.c @@ -1,41 +1,103 @@ /* - * DaVinci pin multiplexing configurations + * Utility to set the DAVINCI MUX register from a table in mux.h * * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> * + * Based on linux/arch/arm/plat-omap/mux.c: + * Copyright (C) 2003 - 2005 Nokia Corporation + * + * Written by Tony Lindgren + * * 2007 (c) MontaVista Software, Inc. This file is licensed under * the terms of the GNU General Public License version 2. This program * is licensed "as is" without any warranty of any kind, whether express * or implied. + * + * Copyright (C) 2008 Texas Instruments. */ #include <linux/io.h> +#include <linux/module.h> #include <linux/spinlock.h> #include <mach/hardware.h> - #include <mach/mux.h> -/* System control register offsets */ -#define PINMUX0 0x00 -#define PINMUX1 0x04 +static const struct mux_config *mux_table; +static unsigned long pin_table_sz; + +int __init davinci_mux_register(const struct mux_config *pins, + unsigned long size) +{ + mux_table = pins; + pin_table_sz = size; -static DEFINE_SPINLOCK(mux_lock); + return 0; +} -void davinci_mux_peripheral(unsigned int mux, unsigned int enable) +/* + * Sets the DAVINCI MUX register based on the table + */ +int __init_or_module davinci_cfg_reg(const unsigned long index) { - u32 pinmux, muxreg = PINMUX0; + static DEFINE_SPINLOCK(mux_spin_lock); + void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); + unsigned long flags; + const struct mux_config *cfg; + unsigned int reg_orig = 0, reg = 0; + unsigned int mask, warn = 0; + + if (!mux_table) + BUG(); + + if (index >= pin_table_sz) { + printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", + index, pin_table_sz); + dump_stack(); + return -ENODEV; + } + + cfg = &mux_table[index]; + + if (cfg->name == NULL) { + printk(KERN_ERR "No entry for the specified index\n"); + return -ENODEV; + } + + /* Update the mux register in question */ + if (cfg->mask) { + unsigned tmp1, tmp2; + + spin_lock_irqsave(&mux_spin_lock, flags); + reg_orig = __raw_readl(base + cfg->mux_reg); + + mask = (cfg->mask << cfg->mask_offset); + tmp1 = reg_orig & mask; + reg = reg_orig & ~mask; + + tmp2 = (cfg->mode << cfg->mask_offset); + reg |= tmp2; + + if (tmp1 != tmp2) + warn = 1; + + __raw_writel(reg, base + cfg->mux_reg); + spin_unlock_irqrestore(&mux_spin_lock, flags); + } + + if (warn) { +#ifdef CONFIG_DAVINCI_MUX_WARNINGS + printk(KERN_WARNING "MUX: initialized %s\n", cfg->name); +#endif + } - if (mux >= DAVINCI_MUX_LEVEL2) { - muxreg = PINMUX1; - mux -= DAVINCI_MUX_LEVEL2; +#ifdef CONFIG_DAVINCI_MUX_DEBUG + if (cfg->debug || warn) { + printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name); + printk(KERN_WARNING " %s (0x%08x) = 0x%08x -> 0x%08x\n", + cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); } +#endif - spin_lock(&mux_lock); - pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg); - if (enable) - pinmux |= (1 << mux); - else - pinmux &= ~(1 << mux); - davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg); - spin_unlock(&mux_lock); + return 0; } +EXPORT_SYMBOL(davinci_cfg_reg); diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h new file mode 100644 index 0000000..adc8694 --- /dev/null +++ b/arch/arm/mach-davinci/mux.h @@ -0,0 +1,51 @@ +/* + * Pin-multiplex helper macros for TI DaVinci family devices + * + * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright (C) 2008 Texas Instruments. + */ +#ifndef _MACH_DAVINCI_MUX_H_ +#define _MACH_DAVINCI_MUX_H_ + +#include <mach/mux.h> + +#define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\ +[soc##_##desc] = { \ + .name = #desc, \ + .debug = dbg, \ + .mux_reg_name = "PINMUX"#muxreg, \ + .mux_reg = PINMUX##muxreg, \ + .mask_offset = mode_offset, \ + .mask = mode_mask, \ + .mode = mux_mode, \ + }, + +#define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \ +[soc##_##desc] = { \ + .name = #desc, \ + .debug = dbg, \ + .mux_reg_name = "INTMUX", \ + .mux_reg = INTMUX, \ + .mask_offset = mode_offset, \ + .mask = mode_mask, \ + .mode = mux_mode, \ + }, + +#define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \ +[soc##_##desc] = { \ + .name = #desc, \ + .debug = dbg, \ + .mux_reg_name = "EVTMUX", \ + .mux_reg = EVTMUX, \ + .mask_offset = mode_offset, \ + .mask = mode_mask, \ + .mode = mux_mode, \ + }, + +#endif /* _MACH_DAVINCI_MUX_H */ diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index 58754f0..84171ab 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -23,10 +23,13 @@ #include <linux/init.h> #include <linux/io.h> +#include <mach/cputype.h> #include <mach/hardware.h> #include <mach/psc.h> #include <mach/mux.h> +#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 + /* PSC register offsets */ #define EPCPR 0x070 #define PTCMD 0x120 @@ -36,102 +39,61 @@ #define MDSTAT 0x800 #define MDCTL 0xA00 -/* System control register offsets */ -#define VDD3P3V_PWDN 0x48 +#define MDSTAT_STATE_MASK 0x1f -static void davinci_psc_mux(unsigned int id) +/* Return nonzero iff the domain's clock is active */ +int __init davinci_psc_is_clk_active(unsigned int id) { - switch (id) { - case DAVINCI_LPSC_ATA: - davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1); - davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1); - break; - case DAVINCI_LPSC_MMC_SD: - /* VDD power manupulations are done in U-Boot for CPMAC - * so applies to MMC as well - */ - /*Set up the pull regiter for MMC */ - davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN); - davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0); - break; - case DAVINCI_LPSC_I2C: - davinci_mux_peripheral(DAVINCI_MUX_I2C, 1); - break; - case DAVINCI_LPSC_McBSP: - davinci_mux_peripheral(DAVINCI_MUX_ASP, 1); - break; - default: - break; - } + void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE); + u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); + + /* if clocked, state can be "Enable" or "SyncReset" */ + return mdstat & BIT(12); } /* Enable or disable a PSC domain */ void davinci_psc_config(unsigned int domain, unsigned int id, char enable) { - u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask; + u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; + void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE); + u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */ - mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id); - if (enable) - mdctl |= 0x00000003; /* Enable Module */ - else - mdctl &= 0xFFFFFFF2; /* Disable Module */ - davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id); + mdctl = __raw_readl(psc_base + MDCTL + 4 * id); + mdctl &= ~MDSTAT_STATE_MASK; + mdctl |= next_state; + __raw_writel(mdctl, psc_base + MDCTL + 4 * id); - pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT); + pdstat = __raw_readl(psc_base + PDSTAT); if ((pdstat & 0x00000001) == 0) { - pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); + pdctl1 = __raw_readl(psc_base + PDCTL1); pdctl1 |= 0x1; - davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); + __raw_writel(pdctl1, psc_base + PDCTL1); ptcmd = 1 << domain; - davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); + __raw_writel(ptcmd, psc_base + PTCMD); do { - epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + - EPCPR); + epcpr = __raw_readl(psc_base + EPCPR); } while ((((epcpr >> domain) & 1) == 0)); - pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); + pdctl1 = __raw_readl(psc_base + PDCTL1); pdctl1 |= 0x100; - davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); + __raw_writel(pdctl1, psc_base + PDCTL1); do { - ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + + ptstat = __raw_readl(psc_base + PTSTAT); } while (!(((ptstat >> domain) & 1) == 0)); } else { ptcmd = 1 << domain; - davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); + __raw_writel(ptcmd, psc_base + PTCMD); do { - ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + - PTSTAT); + ptstat = __raw_readl(psc_base + PTSTAT); } while (!(((ptstat >> domain) & 1) == 0)); } - if (enable) - mdstat_mask = 0x3; - else - mdstat_mask = 0x2; - do { - mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + - MDSTAT + 4 * id); - } while (!((mdstat & 0x0000001F) == mdstat_mask)); - - if (enable) - davinci_psc_mux(id); -} - -void __init davinci_psc_init(void) -{ - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSMSTR, 1); - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSSLV, 1); - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPCC, 1); - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC0, 1); - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC1, 1); - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_GPIO, 1); - - /* Turn on WatchDog timer LPSC. Needed for RESET to work */ - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TIMER2, 1); + mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); + } while (!((mdstat & MDSTAT_STATE_MASK) == next_state)); } diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c index 3010f99..6950757 100644 --- a/arch/arm/mach-davinci/serial.c +++ b/arch/arm/mach-davinci/serial.c @@ -32,32 +32,47 @@ #include <mach/hardware.h> #include <mach/serial.h> #include <mach/irqs.h> +#include <mach/cputype.h> +#include "clock.h" -#define UART_DAVINCI_PWREMU 0x0c - -static inline unsigned int davinci_serial_in(struct plat_serial8250_port *up, - int offset) +static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, + int offset) { offset <<= up->regshift; - return (unsigned int)__raw_readb(up->membase + offset); + return (unsigned int)__raw_readl(IO_ADDRESS(up->mapbase) + offset); } -static inline void davinci_serial_outp(struct plat_serial8250_port *p, - int offset, int value) +static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, + int value) { offset <<= p->regshift; - __raw_writeb(value, p->membase + offset); + __raw_writel(value, IO_ADDRESS(p->mapbase) + offset); } static struct plat_serial8250_port serial_platform_data[] = { { - .membase = (char *)IO_ADDRESS(DAVINCI_UART0_BASE), - .mapbase = (unsigned long)DAVINCI_UART0_BASE, + .mapbase = DAVINCI_UART0_BASE, .irq = IRQ_UARTINT0, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART1_BASE, + .irq = IRQ_UARTINT1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART2_BASE, + .irq = IRQ_UARTINT2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = 27000000, }, { .flags = 0 @@ -74,22 +89,68 @@ static struct platform_device serial_device = { static void __init davinci_serial_reset(struct plat_serial8250_port *p) { - /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */ unsigned int pwremu = 0; - davinci_serial_outp(p, UART_IER, 0); /* disable all interrupts */ + serial_write_reg(p, UART_IER, 0); /* disable all interrupts */ - davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); + /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */ + serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu); mdelay(10); pwremu |= (0x3 << 13); pwremu |= 0x1; - davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); + serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu); + + if (cpu_is_davinci_dm646x()) + serial_write_reg(p, UART_DM646X_SCR, + UART_DM646X_SCR_TX_WATERMARK); +} + +void __init davinci_serial_init(struct davinci_uart_config *info) +{ + int i; + char name[16]; + struct clk *uart_clk; + struct device *dev = &serial_device.dev; + + /* + * Make sure the serial ports are muxed on at this point. + * You have to mux them off in device drivers later on + * if not needed. + */ + for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++) { + struct plat_serial8250_port *p = serial_platform_data + i; + + if (!(info->enabled_uarts & (1 << i))) { + p->flags = 0; + continue; + } + + if (cpu_is_davinci_dm646x()) + p->iotype = UPIO_MEM32; + + if (cpu_is_davinci_dm355()) { + if (i == 2) { + p->mapbase = (unsigned long)DM355_UART2_BASE; + p->irq = IRQ_DM355_UARTINT2; + } + } + + sprintf(name, "uart%d", i); + uart_clk = clk_get(dev, name); + if (IS_ERR(uart_clk)) + printk(KERN_ERR "%s:%d: failed to get UART%d clock\n", + __func__, __LINE__, i); + else { + clk_enable(uart_clk); + p->uartclk = clk_get_rate(uart_clk); + davinci_serial_reset(p); + } + } } static int __init davinci_init(void) { - davinci_serial_reset(&serial_platform_data[0]); return platform_device_register(&serial_device); } diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 6c227d4..494e01b 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -16,6 +16,9 @@ #include <linux/clockchips.h> #include <linux/spinlock.h> #include <linux/io.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/device.h> #include <mach/hardware.h> #include <asm/system.h> @@ -24,8 +27,11 @@ #include <asm/mach/time.h> #include <asm/errno.h> #include <mach/io.h> +#include <mach/cputype.h> +#include "clock.h" static struct clock_event_device clockevent_davinci; +static unsigned int davinci_clock_tick_rate; #define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) #define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) @@ -99,9 +105,9 @@ struct timer_s { unsigned int id; unsigned long period; unsigned long opts; - unsigned long reg_base; - unsigned long tim_reg; - unsigned long prd_reg; + void __iomem *base; + unsigned long tim_off; + unsigned long prd_off; unsigned long enamode_shift; struct irqaction irqaction; }; @@ -114,15 +120,15 @@ static struct timer_s timers[]; static int timer32_config(struct timer_s *t) { - u32 tcr = davinci_readl(t->reg_base + TCR); + u32 tcr = __raw_readl(t->base + TCR); /* disable timer */ tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); - davinci_writel(tcr, t->reg_base + TCR); + __raw_writel(tcr, t->base + TCR); /* reset counter to zero, set new period */ - davinci_writel(0, t->tim_reg); - davinci_writel(t->period, t->prd_reg); + __raw_writel(0, t->base + t->tim_off); + __raw_writel(t->period, t->base + t->prd_off); /* Set enable mode */ if (t->opts & TIMER_OPTS_ONESHOT) { @@ -131,13 +137,13 @@ static int timer32_config(struct timer_s *t) tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; } - davinci_writel(tcr, t->reg_base + TCR); + __raw_writel(tcr, t->base + TCR); return 0; } static inline u32 timer32_read(struct timer_s *t) { - return davinci_readl(t->tim_reg); + return __raw_readl(t->base + t->tim_off); } static irqreturn_t timer_interrupt(int irq, void *dev_id) @@ -176,51 +182,54 @@ static struct timer_s timers[] = { static void __init timer_init(void) { - u32 bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE}; + u32 phys_bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE}; int i; /* Global init of each 64-bit timer as a whole */ for(i=0; i<2; i++) { - u32 tgcr, base = bases[i]; + u32 tgcr; + void __iomem *base = IO_ADDRESS(phys_bases[i]); /* Disabled, Internal clock source */ - davinci_writel(0, base + TCR); + __raw_writel(0, base + TCR); /* reset both timers, no pre-scaler for timer34 */ tgcr = 0; - davinci_writel(tgcr, base + TGCR); + __raw_writel(tgcr, base + TGCR); /* Set both timers to unchained 32-bit */ tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; - davinci_writel(tgcr, base + TGCR); + __raw_writel(tgcr, base + TGCR); /* Unreset timers */ tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - davinci_writel(tgcr, base + TGCR); + __raw_writel(tgcr, base + TGCR); /* Init both counters to zero */ - davinci_writel(0, base + TIM12); - davinci_writel(0, base + TIM34); + __raw_writel(0, base + TIM12); + __raw_writel(0, base + TIM34); } /* Init of each timer as a 32-bit timer */ for (i=0; i< ARRAY_SIZE(timers); i++) { struct timer_s *t = &timers[i]; + u32 phys_base; if (t->name) { t->id = i; - t->reg_base = (IS_TIMER1(t->id) ? + phys_base = (IS_TIMER1(t->id) ? DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE); + t->base = IO_ADDRESS(phys_base); if (IS_TIMER_BOT(t->id)) { t->enamode_shift = 6; - t->tim_reg = t->reg_base + TIM12; - t->prd_reg = t->reg_base + PRD12; + t->tim_off = TIM12; + t->prd_off = PRD12; } else { t->enamode_shift = 22; - t->tim_reg = t->reg_base + TIM34; - t->prd_reg = t->reg_base + PRD34; + t->tim_off = TIM34; + t->prd_off = PRD34; } /* Register interrupt */ @@ -274,7 +283,7 @@ static void davinci_set_mode(enum clock_event_mode mode, switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - t->period = CLOCK_TICK_RATE / (HZ); + t->period = davinci_clock_tick_rate / (HZ); t->opts = TIMER_OPTS_PERIODIC; timer32_config(t); break; @@ -301,21 +310,29 @@ static struct clock_event_device clockevent_davinci = { static void __init davinci_timer_init(void) { + struct clk *timer_clk; + static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; /* init timer hw */ timer_init(); + timer_clk = clk_get(NULL, "timer0"); + BUG_ON(IS_ERR(timer_clk)); + clk_enable(timer_clk); + + davinci_clock_tick_rate = clk_get_rate(timer_clk); + /* setup clocksource */ clocksource_davinci.mult = - clocksource_khz2mult(CLOCK_TICK_RATE/1000, + clocksource_khz2mult(davinci_clock_tick_rate/1000, clocksource_davinci.shift); if (clocksource_register(&clocksource_davinci)) printk(err, clocksource_davinci.name); /* setup clockevent */ - clockevent_davinci.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, + clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC, clockevent_davinci.shift); clockevent_davinci.max_delta_ns = clockevent_delta2ns(0xfffffffe, &clockevent_davinci); @@ -333,42 +350,52 @@ struct sys_timer davinci_timer = { /* reset board using watchdog timer */ void davinci_watchdog_reset(void) { - u32 tgcr, wdtcr, base = DAVINCI_WDOG_BASE; + u32 tgcr, wdtcr; + void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE); + struct device dev; + struct clk *wd_clk; + char *name = "watchdog"; + + dev_set_name(&dev, name); + wd_clk = clk_get(&dev, NULL); + if (WARN_ON(IS_ERR(wd_clk))) + return; + clk_enable(wd_clk); /* disable, internal clock source */ - davinci_writel(0, base + TCR); + __raw_writel(0, base + TCR); /* reset timer, set mode to 64-bit watchdog, and unreset */ tgcr = 0; - davinci_writel(tgcr, base + TCR); + __raw_writel(tgcr, base + TCR); tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - davinci_writel(tgcr, base + TCR); + __raw_writel(tgcr, base + TCR); /* clear counter and period regs */ - davinci_writel(0, base + TIM12); - davinci_writel(0, base + TIM34); - davinci_writel(0, base + PRD12); - davinci_writel(0, base + PRD34); + __raw_writel(0, base + TIM12); + __raw_writel(0, base + TIM34); + __raw_writel(0, base + PRD12); + __raw_writel(0, base + PRD34); /* enable */ - wdtcr = davinci_readl(base + WDTCR); + wdtcr = __raw_readl(base + WDTCR); wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT; - davinci_writel(wdtcr, base + WDTCR); + __raw_writel(wdtcr, base + WDTCR); /* put watchdog in pre-active state */ wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); - davinci_writel(wdtcr, base + WDTCR); + __raw_writel(wdtcr, base + WDTCR); /* put watchdog in active state */ wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); - davinci_writel(wdtcr, base + WDTCR); + __raw_writel(wdtcr, base + WDTCR); /* write an invalid value to the WDKEY field to trigger * a watchdog reset */ wdtcr = 0x00004000; - davinci_writel(wdtcr, base + WDTCR); + __raw_writel(wdtcr, base + WDTCR); } diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c index 2429b79..abedb63 100644 --- a/arch/arm/mach-davinci/usb.c +++ b/arch/arm/mach-davinci/usb.c @@ -14,6 +14,8 @@ #include <mach/hardware.h> #include <mach/irqs.h> +#define DAVINCI_USB_OTG_BASE 0x01C64000 + #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) static struct musb_hdrc_eps_bits musb_eps[] = { { "ep1_tx", 8, }, diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c index 44d4a96..46098f5 100644 --- a/arch/arm/mach-omap1/board-h2-mmc.c +++ b/arch/arm/mach-omap1/board-h2-mmc.c @@ -26,19 +26,13 @@ static int mmc_set_power(struct device *dev, int slot, int power_on, int vdd) { - if (power_on) - gpio_direction_output(H2_TPS_GPIO_MMC_PWR_EN, 1); - else - gpio_direction_output(H2_TPS_GPIO_MMC_PWR_EN, 0); - + gpio_set_value(H2_TPS_GPIO_MMC_PWR_EN, power_on); return 0; } static int mmc_late_init(struct device *dev) { - int ret; - - ret = gpio_request(H2_TPS_GPIO_MMC_PWR_EN, "MMC power"); + int ret = gpio_request(H2_TPS_GPIO_MMC_PWR_EN, "MMC power"); if (ret < 0) return ret; @@ -47,7 +41,7 @@ static int mmc_late_init(struct device *dev) return ret; } -static void mmc_shutdown(struct device *dev) +static void mmc_cleanup(struct device *dev) { gpio_free(H2_TPS_GPIO_MMC_PWR_EN); } @@ -60,7 +54,7 @@ static void mmc_shutdown(struct device *dev) static struct omap_mmc_platform_data mmc1_data = { .nr_slots = 1, .init = mmc_late_init, - .shutdown = mmc_shutdown, + .cleanup = mmc_cleanup, .dma_mask = 0xffffffff, .slots[0] = { .set_power = mmc_set_power, diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c index 0d8a3c1..5e8877c 100644 --- a/arch/arm/mach-omap1/board-h3-mmc.c +++ b/arch/arm/mach-omap1/board-h3-mmc.c @@ -26,11 +26,7 @@ static int mmc_set_power(struct device *dev, int slot, int power_on, int vdd) { - if (power_on) - gpio_direction_output(H3_TPS_GPIO_MMC_PWR_EN, 1); - else - gpio_direction_output(H3_TPS_GPIO_MMC_PWR_EN, 0); - + gpio_set_value(H3_TPS_GPIO_MMC_PWR_EN, power_on); return 0; } diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 4695965..f597968 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -39,12 +39,10 @@ #include <asm/mach/flash.h> #include <asm/mach/map.h> -#include <mach/gpioexpander.h> #include <mach/irqs.h> #include <mach/mux.h> #include <mach/tc.h> #include <mach/nand.h> -#include <mach/irda.h> #include <mach/usb.h> #include <mach/keypad.h> #include <mach/dma.h> @@ -276,104 +274,6 @@ static struct platform_device h3_kp_device = { .resource = h3_kp_resources, }; - -/* Select between the IrDA and aGPS module - */ -static int h3_select_irda(struct device *dev, int state) -{ - unsigned char expa; - int err = 0; - - if ((err = read_gpio_expa(&expa, 0x26))) { - printk(KERN_ERR "Error reading from I/O EXPANDER \n"); - return err; - } - - /* 'P6' enable/disable IRDA_TX and IRDA_RX */ - if (state & IR_SEL) { /* IrDA */ - if ((err = write_gpio_expa(expa | 0x40, 0x26))) { - printk(KERN_ERR "Error writing to I/O EXPANDER \n"); - return err; - } - } else { - if ((err = write_gpio_expa(expa & ~0x40, 0x26))) { - printk(KERN_ERR "Error writing to I/O EXPANDER \n"); - return err; - } - } - return err; -} - -static void set_trans_mode(struct work_struct *work) -{ - struct omap_irda_config *irda_config = - container_of(work, struct omap_irda_config, gpio_expa.work); - int mode = irda_config->mode; - unsigned char expa; - int err = 0; - - if ((err = read_gpio_expa(&expa, 0x27)) != 0) { - printk(KERN_ERR "Error reading from I/O expander\n"); - } - - expa &= ~0x03; - - if (mode & IR_SIRMODE) { - expa |= 0x01; - } else { /* MIR/FIR */ - expa |= 0x03; - } - - if ((err = write_gpio_expa(expa, 0x27)) != 0) { - printk(KERN_ERR "Error writing to I/O expander\n"); - } -} - -static int h3_transceiver_mode(struct device *dev, int mode) -{ - struct omap_irda_config *irda_config = dev->platform_data; - - irda_config->mode = mode; - cancel_delayed_work(&irda_config->gpio_expa); - PREPARE_DELAYED_WORK(&irda_config->gpio_expa, set_trans_mode); - schedule_delayed_work(&irda_config->gpio_expa, 0); - - return 0; -} - -static struct omap_irda_config h3_irda_data = { - .transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE, - .transceiver_mode = h3_transceiver_mode, - .select_irda = h3_select_irda, - .rx_channel = OMAP_DMA_UART3_RX, - .tx_channel = OMAP_DMA_UART3_TX, - .dest_start = UART3_THR, - .src_start = UART3_RHR, - .tx_trigger = 0, - .rx_trigger = 0, -}; - -static struct resource h3_irda_resources[] = { - [0] = { - .start = INT_UART3, - .end = INT_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 irda_dmamask = 0xffffffff; - -static struct platform_device h3_irda_device = { - .name = "omapirda", - .id = 0, - .dev = { - .platform_data = &h3_irda_data, - .dma_mask = &irda_dmamask, - }, - .num_resources = ARRAY_SIZE(h3_irda_resources), - .resource = h3_irda_resources, -}; - static struct platform_device h3_lcd_device = { .name = "lcd_h3", .id = -1, @@ -395,7 +295,6 @@ static struct platform_device *devices[] __initdata = { &nand_device, &smc91x_device, &intlat_device, - &h3_irda_device, &h3_kp_device, &h3_lcd_device, }; diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 7bc7a3c..d1ed136 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -181,11 +181,7 @@ static struct omap_usb_config nokia770_usb_config __initdata = { static int nokia770_mmc_set_power(struct device *dev, int slot, int power_on, int vdd) { - if (power_on) - gpio_set_value(NOKIA770_GPIO_MMC_POWER, 1); - else - gpio_set_value(NOKIA770_GPIO_MMC_POWER, 0); - + gpio_set_value(NOKIA770_GPIO_MMC_POWER, power_on); return 0; } diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index d040c3f..a2d7814 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -40,8 +40,8 @@ static void omap1_mcbsp_request(unsigned int id) */ if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { if (dsp_use++ == 0) { - api_clk = clk_get(NULL, "api_clk"); - dsp_clk = clk_get(NULL, "dsp_clk"); + api_clk = clk_get(NULL, "api_ck"); + dsp_clk = clk_get(NULL, "dsp_ck"); if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) { clk_enable(api_clk); clk_enable(dsp_clk); diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index a0267a9..e7d017c 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -33,10 +33,8 @@ #include <mach/control.h> #include <mach/gpio.h> -#include <mach/gpioexpander.h> #include <mach/mux.h> #include <mach/usb.h> -#include <mach/irda.h> #include <mach/board.h> #include <mach/common.h> #include <mach/keypad.h> @@ -138,98 +136,6 @@ static struct platform_device h4_flash_device = { .resource = &h4_flash_resource, }; -/* Select between the IrDA and aGPS module - */ -static int h4_select_irda(struct device *dev, int state) -{ - unsigned char expa; - int err = 0; - - if ((err = read_gpio_expa(&expa, 0x21))) { - printk(KERN_ERR "Error reading from I/O expander\n"); - return err; - } - - /* 'P6' enable/disable IRDA_TX and IRDA_RX */ - if (state & IR_SEL) { /* IrDa */ - if ((err = write_gpio_expa(expa | 0x01, 0x21))) { - printk(KERN_ERR "Error writing to I/O expander\n"); - return err; - } - } else { - if ((err = write_gpio_expa(expa & ~0x01, 0x21))) { - printk(KERN_ERR "Error writing to I/O expander\n"); - return err; - } - } - return err; -} - -static void set_trans_mode(struct work_struct *work) -{ - struct omap_irda_config *irda_config = - container_of(work, struct omap_irda_config, gpio_expa.work); - int mode = irda_config->mode; - unsigned char expa; - int err = 0; - - if ((err = read_gpio_expa(&expa, 0x20)) != 0) { - printk(KERN_ERR "Error reading from I/O expander\n"); - } - - expa &= ~0x01; - - if (!(mode & IR_SIRMODE)) { /* MIR/FIR */ - expa |= 0x01; - } - - if ((err = write_gpio_expa(expa, 0x20)) != 0) { - printk(KERN_ERR "Error writing to I/O expander\n"); - } -} - -static int h4_transceiver_mode(struct device *dev, int mode) -{ - struct omap_irda_config *irda_config = dev->platform_data; - - irda_config->mode = mode; - cancel_delayed_work(&irda_config->gpio_expa); - PREPARE_DELAYED_WORK(&irda_config->gpio_expa, set_trans_mode); - schedule_delayed_work(&irda_config->gpio_expa, 0); - - return 0; -} - -static struct omap_irda_config h4_irda_data = { - .transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE, - .transceiver_mode = h4_transceiver_mode, - .select_irda = h4_select_irda, - .rx_channel = OMAP24XX_DMA_UART3_RX, - .tx_channel = OMAP24XX_DMA_UART3_TX, - .dest_start = OMAP_UART3_BASE, - .src_start = OMAP_UART3_BASE, - .tx_trigger = OMAP24XX_DMA_UART3_TX, - .rx_trigger = OMAP24XX_DMA_UART3_RX, -}; - -static struct resource h4_irda_resources[] = { - [0] = { - .start = INT_24XX_UART3_IRQ, - .end = INT_24XX_UART3_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device h4_irda_device = { - .name = "omapirda", - .id = -1, - .dev = { - .platform_data = &h4_irda_data, - }, - .num_resources = 1, - .resource = h4_irda_resources, -}; - static struct omap_kp_platform_data h4_kp_data = { .rows = 6, .cols = 7, @@ -255,7 +161,6 @@ static struct platform_device h4_lcd_device = { static struct platform_device *h4_devices[] __initdata = { &h4_flash_device, - &h4_irda_device, &h4_kp_device, &h4_lcd_device, }; diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 744740a..3a7a29d 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -42,6 +42,7 @@ #include <mach/nand.h> #include <mach/mux.h> #include <mach/usb.h> +#include <mach/timer-gp.h> #include "mmc-twl4030.h" @@ -186,6 +187,9 @@ static void __init omap3_beagle_init_irq(void) { omap2_init_common_hw(NULL); omap_init_irq(); +#ifdef CONFIG_OMAP_32K_TIMER + omap2_gp_clockevent_set_gptimer(12); +#endif omap_gpio_init(); } diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 3a0daac..374ff63 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -15,7 +15,6 @@ #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> -#include <linux/delay.h> #include <linux/gpio.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index 1e839c5..efc59c4 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -60,12 +60,13 @@ struct omap_clk { }, \ } -#define CK_243X (1 << 0) -#define CK_242X (1 << 1) +#define CK_243X RATE_IN_243X +#define CK_242X RATE_IN_242X static struct omap_clk omap24xx_clks[] = { /* external root sources */ CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X), CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), @@ -711,7 +712,7 @@ int __init omap2_clk_init(void) { struct prcm_config *prcm; struct omap_clk *c; - u32 clkrate, cpu_mask; + u32 clkrate; if (cpu_is_omap242x()) cpu_mask = RATE_IN_242X; @@ -720,21 +721,15 @@ int __init omap2_clk_init(void) clk_init(&omap2_clk_functions); + for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) + clk_init_one(c->lk.clk); + osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); propagate_rate(&osc_ck); sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); propagate_rate(&sys_ck); for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) - clk_init_one(c->lk.clk); - - cpu_mask = 0; - if (cpu_is_omap2420()) - cpu_mask |= CK_242X; - if (cpu_is_omap2430()) - cpu_mask |= CK_243X; - - for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) if (c->cpu & cpu_mask) { clkdev_add(&c->lk); clk_register(c->lk.clk); diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 33c3e5b..88c5acb 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -625,6 +625,14 @@ static struct clk func_32k_ck = { .clkdm_name = "wkup_clkdm", }; +static struct clk secure_32k_ck = { + .name = "secure_32k_ck", + .ops = &clkops_null, + .rate = 32768, + .flags = RATE_FIXED, + .clkdm_name = "wkup_clkdm", +}; + /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ .name = "osc_ck", @@ -1790,7 +1798,7 @@ static struct clk gpt12_ick = { static struct clk gpt12_fck = { .name = "gpt12_fck", .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, + .parent = &secure_32k_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT12_SHIFT, diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 70ec10d..6763b8f 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -2052,7 +2052,7 @@ static struct clk dss_ick = { static struct clk cam_mclk = { .name = "cam_mclk", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &dpll4_m5x2_ck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, @@ -2063,7 +2063,7 @@ static struct clk cam_mclk = { static struct clk cam_ick = { /* Handles both L3 and L4 clocks */ .name = "cam_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &l4_ick, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), @@ -2074,7 +2074,7 @@ static struct clk cam_ick = { static struct clk csi2_96m_fck = { .name = "csi2_96m_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &core_96m_fck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), @@ -2901,7 +2901,6 @@ static struct clk sr_l4_ick = { /* SECURE_32K_FCK clocks */ -/* XXX This clock no longer exists in 3430 TRM rev F */ static struct clk gpt12_fck = { .name = "gpt12_fck", .ops = &clkops_null, diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index d6b4b2f..496983a 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -25,7 +25,6 @@ #include <mach/board.h> #include <mach/mux.h> #include <mach/gpio.h> -#include <mach/eac.h> #include <mach/mmc.h> #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) @@ -366,38 +365,6 @@ static void omap_init_mcspi(void) static inline void omap_init_mcspi(void) {} #endif -#ifdef CONFIG_SND_OMAP24XX_EAC - -#define OMAP2_EAC_BASE 0x48090000 - -static struct resource omap2_eac_resources[] = { - { - .start = OMAP2_EAC_BASE, - .end = OMAP2_EAC_BASE + 0x109, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap2_eac_device = { - .name = "omap24xx-eac", - .id = -1, - .num_resources = ARRAY_SIZE(omap2_eac_resources), - .resource = omap2_eac_resources, - .dev = { - .platform_data = NULL, - }, -}; - -void omap_init_eac(struct eac_platform_data *pdata) -{ - omap2_eac_device.dev.platform_data = pdata; - platform_device_register(&omap2_eac_device); -} - -#else -void omap_init_eac(struct eac_platform_data *pdata) {} -#endif - #ifdef CONFIG_OMAP_SHA1_MD5 static struct resource sha1_md5_resources[] = { { diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 9ba20d9..998c5c4 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -73,9 +73,9 @@ static int omap_check_spurious(unsigned int irq) u32 sir, spurious; sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR); - spurious = sir >> 6; + spurious = sir >> 7; - if (spurious > 1) { + if (spurious) { printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush " "posted write for irq %i\n", irq, sir, previous_irq); diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index 1cb2c09..f36aba1 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -3,6 +3,8 @@ * * OMAP2 GP timer support. * + * Copyright (C) 2009 Nokia Corporation + * * Update to use new clocksource/clockevent layers * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> * Copyright (C) 2007 MontaVista Software, Inc. @@ -36,8 +38,13 @@ #include <asm/mach/time.h> #include <mach/dmtimer.h> +/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ +#define MAX_GPTIMER_ID 12 + static struct omap_dm_timer *gptimer; static struct clock_event_device clockevent_gpt; +static u8 __initdata gptimer_id = 1; +static u8 __initdata inited; static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) { @@ -95,20 +102,53 @@ static struct clock_event_device clockevent_gpt = { .set_mode = omap2_gp_timer_set_mode, }; +/** + * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents + * @id: GPTIMER to use (1..MAX_GPTIMER_ID) + * + * Define the GPTIMER that the system should use for the tick timer. + * Meant to be called from board-*.c files in the event that GPTIMER1, the + * default, is unsuitable. Returns -EINVAL on error or 0 on success. + */ +int __init omap2_gp_clockevent_set_gptimer(u8 id) +{ + if (id < 1 || id > MAX_GPTIMER_ID) + return -EINVAL; + + BUG_ON(inited); + + gptimer_id = id; + + return 0; +} + static void __init omap2_gp_clockevent_init(void) { u32 tick_rate; + int src; + + inited = 1; - gptimer = omap_dm_timer_request_specific(1); + gptimer = omap_dm_timer_request_specific(gptimer_id); BUG_ON(gptimer == NULL); #if defined(CONFIG_OMAP_32K_TIMER) - omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ); + src = OMAP_TIMER_SRC_32_KHZ; #else - omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); + src = OMAP_TIMER_SRC_SYS_CLK; + WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the " + "secure 32KiHz clock source\n"); #endif + + if (gptimer_id != 12) + WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)), + "timer-gp: omap_dm_timer_set_source() failed\n"); + tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); + pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", + gptimer_id, tick_rate); + omap2_gp_timer_irq.dev_id = (void *)gptimer; setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); @@ -125,6 +165,8 @@ static void __init omap2_gp_clockevent_init(void) clockevents_register_device(&clockevent_gpt); } +/* Clocksource code */ + #ifdef CONFIG_OMAP_32K_TIMER /* * When 32k-timer is enabled, don't use GPTimer for clocksource diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 15e5090..8df55f4 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -187,7 +187,7 @@ int tusb6010_platform_retime(unsigned is_refclk) unsigned sysclk_ps; int status; - if (!refclk_psec) + if (!refclk_psec || sysclk_ps == 0) return -ENODEV; sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60; diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index cdf21dd..930e364 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -427,12 +427,22 @@ static struct pxa2xx_spi_master corgi_spi_info = { .num_chipselect = 3, }; +static void corgi_wait_for_hsync(void) +{ + while (gpio_get_value(CORGI_GPIO_HSYNC)) + cpu_relax(); + + while (!gpio_get_value(CORGI_GPIO_HSYNC)) + cpu_relax(); +} + static struct ads7846_platform_data corgi_ads7846_info = { .model = 7846, .vref_delay_usecs = 100, .x_plate_ohms = 419, .y_plate_ohms = 486, .gpio_pendown = CORGI_GPIO_TP_INT, + .wait_for_sync = corgi_wait_for_hsync, }; static void corgi_ads7846_cs(u32 command) diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index e13f6a8..c872b9f 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -334,6 +334,11 @@ static struct led_info littleton_da9034_leds[] = { }, }; +static struct da9034_touch_pdata littleton_da9034_touch = { + .x_inverted = 1, + .interval_ms = 20, +}; + static struct da903x_subdev_info littleton_da9034_subdevs[] = { { .name = "da903x-led", @@ -350,6 +355,10 @@ static struct da903x_subdev_info littleton_da9034_subdevs[] = { }, { .name = "da903x-backlight", .id = DA9034_ID_WLED, + }, { + .name = "da9034-touch", + .id = DA9034_ID_TOUCH, + .platform_data = &littleton_da9034_touch, }, }; diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 8c61dda..c18e34a 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -299,12 +299,22 @@ static struct pxa2xx_spi_master spitz_spi_info = { .num_chipselect = 3, }; +static void spitz_wait_for_hsync(void) +{ + while (gpio_get_value(SPITZ_GPIO_HSYNC)) + cpu_relax(); + + while (!gpio_get_value(SPITZ_GPIO_HSYNC)) + cpu_relax(); +} + static struct ads7846_platform_data spitz_ads7846_info = { .model = 7846, .vref_delay_usecs = 100, .x_plate_ohms = 419, .y_plate_ohms = 486, .gpio_pendown = SPITZ_GPIO_TP_INT, + .wait_for_sync = spitz_wait_for_hsync, }; static void spitz_ads7846_cs(u32 command) diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c index c1f7320..c256c57 100644 --- a/arch/arm/mach-pxa/zylonite_pxa300.c +++ b/arch/arm/mach-pxa/zylonite_pxa300.c @@ -72,6 +72,7 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = { GPIO25_AC97_SDATA_IN_0, GPIO27_AC97_SDATA_OUT, GPIO28_AC97_SYNC, + GPIO17_GPIO, /* SDATA_IN_1 but unused - configure to GPIO */ /* SSP3 */ GPIO91_SSP3_SCLK, @@ -126,6 +127,10 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = { /* Standard I2C */ GPIO21_I2C_SCL, GPIO22_I2C_SDA, + + /* GPIO */ + GPIO18_GPIO, /* GPIO Expander #0 INT_N */ + GPIO19_GPIO, /* GPIO Expander #1 INT_N */ }; static mfp_cfg_t pxa300_mfp_cfg[] __initdata = { diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c index 4e1c488..cc5a228 100644 --- a/arch/arm/mach-pxa/zylonite_pxa320.c +++ b/arch/arm/mach-pxa/zylonite_pxa320.c @@ -68,6 +68,7 @@ static mfp_cfg_t mfp_cfg[] __initdata = { GPIO38_AC97_SYNC, GPIO39_AC97_BITCLK, GPIO40_AC97_nACRESET, + GPIO36_GPIO, /* SDATA_IN_1 but unused - configure to GPIO */ /* SSP3 */ GPIO89_SSP3_SCLK, diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c index 0cd5269..1f940df 100644 --- a/arch/arm/mach-sa1100/lart.c +++ b/arch/arm/mach-sa1100/lart.c @@ -9,6 +9,7 @@ #include <mach/hardware.h> #include <asm/setup.h> #include <asm/mach-types.h> +#include <asm/page.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 2c6c2a7..8f5c13f 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -20,6 +20,31 @@ #define D_CACHE_LINE_SIZE 32 #define BTB_FLUSH_SIZE 8 +#ifdef CONFIG_ARM_ERRATA_411920 +/* + * Invalidate the entire I cache (this code is a workaround for the ARM1136 + * erratum 411920 - Invalidate Instruction Cache operation can fail. This + * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore. + * + * Registers: + * r0 - set to 0 + * r1 - corrupted + */ +ENTRY(v6_icache_inval_all) + mov r0, #0 + mrs r1, cpsr + cpsid ifa @ disable interrupts + mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache + mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache + mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache + mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache + msr cpsr_cx, r1 @ restore interrupts + .rept 11 @ ARM Ltd recommends at least + nop @ 11 NOPs + .endr + mov pc, lr +#endif + /* * v6_flush_cache_all() * @@ -31,8 +56,12 @@ ENTRY(v6_flush_kern_cache_all) mov r0, #0 #ifdef HARVARD_CACHE mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate +#ifndef CONFIG_ARM_ERRATA_411920 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate #else + b v6_icache_inval_all +#endif +#else mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate #endif mov pc, lr @@ -103,8 +132,12 @@ ENTRY(v6_coherent_user_range) mov r0, #0 #ifdef HARVARD_CACHE mcr p15, 0, r0, c7, c10, 4 @ drain write buffer +#ifndef CONFIG_ARM_ERRATA_411920 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate #else + b v6_icache_inval_all +#endif +#else mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB #endif mov pc, lr diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 4e28348..c07222e 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -18,6 +18,10 @@ #include "mm.h" +#ifdef CONFIG_ARM_ERRATA_411920 +extern void v6_icache_inval_all(void); +#endif + #ifdef CONFIG_CPU_CACHE_VIPT #define ALIAS_FLUSH_START 0xffff4000 @@ -32,10 +36,15 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) asm( "mcrr p15, 0, %1, %0, c14\n" " mcr p15, 0, %2, c7, c10, 4\n" +#ifndef CONFIG_ARM_ERRATA_411920 " mcr p15, 0, %2, c7, c5, 0\n" +#endif : : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) : "cc"); +#ifdef CONFIG_ARM_ERRATA_411920 + v6_icache_inval_all(); +#endif } void flush_cache_mm(struct mm_struct *mm) @@ -48,11 +57,16 @@ void flush_cache_mm(struct mm_struct *mm) if (cache_is_vipt_aliasing()) { asm( "mcr p15, 0, %0, c7, c14, 0\n" + " mcr p15, 0, %0, c7, c10, 4\n" +#ifndef CONFIG_ARM_ERRATA_411920 " mcr p15, 0, %0, c7, c5, 0\n" - " mcr p15, 0, %0, c7, c10, 4" +#endif : : "r" (0) : "cc"); +#ifdef CONFIG_ARM_ERRATA_411920 + v6_icache_inval_all(); +#endif } } @@ -67,11 +81,16 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned if (cache_is_vipt_aliasing()) { asm( "mcr p15, 0, %0, c7, c14, 0\n" + " mcr p15, 0, %0, c7, c10, 4\n" +#ifndef CONFIG_ARM_ERRATA_411920 " mcr p15, 0, %0, c7, c5, 0\n" - " mcr p15, 0, %0, c7, c10, 4" +#endif : : "r" (0) : "cc"); +#ifdef CONFIG_ARM_ERRATA_411920 + v6_icache_inval_all(); +#endif } } diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c221e26..3397f1e 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -96,6 +96,9 @@ ENTRY(cpu_v7_switch_mm) mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id orr r0, r0, #TTB_FLAGS +#ifdef CONFIG_ARM_ERRATA_430973 + mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB +#endif mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID isb 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 @@ -181,6 +184,22 @@ __v7_setup: stmia r12, {r0-r5, r7, r9, r11, lr} bl v7_flush_dcache_all ldmia r12, {r0-r5, r7, r9, r11, lr} +#ifdef CONFIG_ARM_ERRATA_430973 + mrc p15, 0, r10, c1, c0, 1 @ read aux control register + orr r10, r10, #(1 << 6) @ set IBE to 1 + mcr p15, 0, r10, c1, c0, 1 @ write aux control register +#endif +#ifdef CONFIG_ARM_ERRATA_458693 + mrc p15, 0, r10, c1, c0, 1 @ read aux control register + orr r10, r10, #(1 << 5) @ set L1NEON to 1 + orr r10, r10, #(1 << 9) @ set PLDNOP to 1 + mcr p15, 0, r10, c1, c0, 1 @ write aux control register +#endif +#ifdef CONFIG_ARM_ERRATA_460075 + mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register + orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit + mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register +#endif mov r10, #0 #ifdef HARVARD_CACHE mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 2e06145..29efc27 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -239,6 +239,13 @@ void recalculate_root_clocks(void) } } +/** + * clk_init_one - initialize any fields in the struct clk before clk init + * @clk: struct clk * to initialize + * + * Initialize any struct clk fields needed before normal clk initialization + * can run. No return value. + */ void clk_init_one(struct clk *clk) { INIT_LIST_HEAD(&clk->children); diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 21cc014..7fc8c04 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -760,19 +760,12 @@ void omap_free_dma(int lch) { unsigned long flags; - spin_lock_irqsave(&dma_chan_lock, flags); if (dma_chan[lch].dev_id == -1) { pr_err("omap_dma: trying to free unallocated DMA channel %d\n", lch); - spin_unlock_irqrestore(&dma_chan_lock, flags); return; } - dma_chan[lch].dev_id = -1; - dma_chan[lch].next_lch = -1; - dma_chan[lch].callback = NULL; - spin_unlock_irqrestore(&dma_chan_lock, flags); - if (cpu_class_is_omap1()) { /* Disable all DMA interrupts for the channel. */ dma_write(0, CICR(lch)); @@ -798,6 +791,12 @@ void omap_free_dma(int lch) dma_write(0, CCR(lch)); omap_clear_dma(lch); } + + spin_lock_irqsave(&dma_chan_lock, flags); + dma_chan[lch].dev_id = -1; + dma_chan[lch].next_lch = -1; + dma_chan[lch].callback = NULL; + spin_unlock_irqrestore(&dma_chan_lock, flags); } EXPORT_SYMBOL(omap_free_dma); diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index bfd4757..55bb996 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -238,7 +238,7 @@ static struct omap_dm_timer omap3_dm_timers[] = { { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 }, { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 }, { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 }, - { .phys_base = 0x48304000, .irq = INT_24XX_GPTIMER12 }, + { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ }, }; static const char *omap3_dm_source_names[] __initdata = { @@ -321,11 +321,9 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer) l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */ /* - * Enable wake-up only for GPT1 on OMAP2 CPUs. - * FIXME: All timers should have wake-up enabled and clear - * PRCM status. + * Enable wake-up on OMAP2 CPUs. */ - if (cpu_class_is_omap2() && (timer == &dm_timers[0])) + if (cpu_class_is_omap2()) l |= 1 << 2; omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l); @@ -511,7 +509,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_stop); #ifdef CONFIG_ARCH_OMAP1 -void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) +int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) { int n = (timer - dm_timers) << 1; u32 l; @@ -519,23 +517,31 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); l |= source << n; omap_writel(l, MOD_CONF_CTRL_1); + + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); #else -void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) +int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) { + int ret = -EINVAL; + if (source < 0 || source >= 3) - return; + return -EINVAL; clk_disable(timer->fclk); - clk_set_parent(timer->fclk, dm_source_clocks[source]); + ret = clk_set_parent(timer->fclk, dm_source_clocks[source]); clk_enable(timer->fclk); - /* When the functional clock disappears, too quick writes seem to - * cause an abort. */ + /* + * When the functional clock disappears, too quick writes seem + * to cause an abort. XXX Is this still necessary? + */ __delay(150000); + + return ret; } EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index d3fa41e..17d7afe 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -758,8 +758,12 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) /* Workaround for clearing DSP GPIO interrupts to allow retention */ #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) + reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; if (cpu_is_omap24xx() || cpu_is_omap34xx()) - __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); + __raw_writel(gpio_mask, reg); + + /* Flush posted write for the irq status to avoid spurious interrupts */ + __raw_readl(reg); #endif } @@ -921,13 +925,10 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) case METHOD_MPUIO: case METHOD_GPIO_1610: spin_lock_irqsave(&bank->lock, flags); - if (enable) { + if (enable) bank->suspend_wakeup |= (1 << gpio); - enable_irq_wake(bank->irq); - } else { - disable_irq_wake(bank->irq); + else bank->suspend_wakeup &= ~(1 << gpio); - } spin_unlock_irqrestore(&bank->lock, flags); return 0; #endif @@ -940,13 +941,10 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) return -EINVAL; } spin_lock_irqsave(&bank->lock, flags); - if (enable) { + if (enable) bank->suspend_wakeup |= (1 << gpio); - enable_irq_wake(bank->irq); - } else { - disable_irq_wake(bank->irq); + else bank->suspend_wakeup &= ~(1 << gpio); - } spin_unlock_irqrestore(&bank->lock, flags); return 0; #endif diff --git a/arch/arm/plat-omap/include/mach/dmtimer.h b/arch/arm/plat-omap/include/mach/dmtimer.h index 6dc70313..20f1054 100644 --- a/arch/arm/plat-omap/include/mach/dmtimer.h +++ b/arch/arm/plat-omap/include/mach/dmtimer.h @@ -64,7 +64,7 @@ void omap_dm_timer_trigger(struct omap_dm_timer *timer); void omap_dm_timer_start(struct omap_dm_timer *timer); void omap_dm_timer_stop(struct omap_dm_timer *timer); -void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); +int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value); void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); diff --git a/arch/arm/plat-omap/include/mach/eac.h b/arch/arm/plat-omap/include/mach/eac.h deleted file mode 100644 index 9e62cf0..0000000 --- a/arch/arm/plat-omap/include/mach/eac.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach2/eac.h - * - * Defines for Enhanced Audio Controller - * - * Contact: Jarkko Nikula <jarkko.nikula@nokia.com> - * - * Copyright (C) 2006 Nokia Corporation - * Copyright (C) 2004 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#ifndef __ASM_ARM_ARCH_OMAP2_EAC_H -#define __ASM_ARM_ARCH_OMAP2_EAC_H - -#include <mach/io.h> -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <sound/core.h> - -/* master codec clock source */ -#define EAC_MCLK_EXT_MASK 0x100 -enum eac_mclk_src { - EAC_MCLK_INT_11290000, /* internal 96 MHz / 8.5 = 11.29 Mhz */ - EAC_MCLK_EXT_11289600 = EAC_MCLK_EXT_MASK, - EAC_MCLK_EXT_12288000, - EAC_MCLK_EXT_2x11289600, - EAC_MCLK_EXT_2x12288000, -}; - -/* codec port interface mode */ -enum eac_codec_mode { - EAC_CODEC_PCM, - EAC_CODEC_AC97, - EAC_CODEC_I2S_MASTER, /* codec port, I.e. EAC is the master */ - EAC_CODEC_I2S_SLAVE, -}; - -/* configuration structure for I2S mode */ -struct eac_i2s_conf { - /* if enabled, then first data slot (left channel) is signaled as - * positive level of frame sync EAC.AC_FS */ - unsigned polarity_changed_mode:1; - /* if enabled, then serial data starts one clock cycle after the - * of EAC.AC_FS for first audio slot */ - unsigned sync_delay_enable:1; -}; - -/* configuration structure for EAC codec port */ -struct eac_codec { - enum eac_mclk_src mclk_src; - - enum eac_codec_mode codec_mode; - union { - struct eac_i2s_conf i2s; - } codec_conf; - - int default_rate; /* audio sampling rate */ - - int (* set_power)(void *private_data, int dac, int adc); - int (* register_controls)(void *private_data, - struct snd_card *card); - const char *short_name; - - void *private_data; -}; - -/* structure for passing platform dependent data to the EAC driver */ -struct eac_platform_data { - int (* init)(struct device *eac_dev); - void (* cleanup)(struct device *eac_dev); - /* these callbacks are used to configure & control external MCLK - * source. NULL if not used */ - int (* enable_ext_clocks)(struct device *eac_dev); - void (* disable_ext_clocks)(struct device *eac_dev); -}; - -extern void omap_init_eac(struct eac_platform_data *pdata); - -extern int eac_register_codec(struct device *eac_dev, struct eac_codec *codec); -extern void eac_unregister_codec(struct device *eac_dev); - -extern int eac_set_mode(struct device *eac_dev, int play, int rec); - -#endif /* __ASM_ARM_ARCH_OMAP2_EAC_H */ diff --git a/arch/arm/plat-omap/include/mach/gpioexpander.h b/arch/arm/plat-omap/include/mach/gpioexpander.h deleted file mode 100644 index 90444a0..0000000 --- a/arch/arm/plat-omap/include/mach/gpioexpander.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/gpioexpander.h - * - * - * Copyright (C) 2004 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef __ASM_ARCH_OMAP_GPIOEXPANDER_H -#define __ASM_ARCH_OMAP_GPIOEXPANDER_H - -/* Function Prototypes for GPIO Expander functions */ - -#ifdef CONFIG_GPIOEXPANDER_OMAP -int read_gpio_expa(u8 *, int); -int write_gpio_expa(u8 , int); -#else -static inline int read_gpio_expa(u8 *val, int addr) -{ - return 0; -} -static inline int write_gpio_expa(u8 val, int addr) -{ - return 0; -} -#endif - -#endif /* __ASM_ARCH_OMAP_GPIOEXPANDER_H */ diff --git a/arch/arm/plat-omap/include/mach/irda.h b/arch/arm/plat-omap/include/mach/irda.h index 8372a00..40f6033 100644 --- a/arch/arm/plat-omap/include/mach/irda.h +++ b/arch/arm/plat-omap/include/mach/irda.h @@ -21,10 +21,6 @@ struct omap_irda_config { int transceiver_cap; int (*transceiver_mode)(struct device *dev, int mode); int (*select_irda)(struct device *dev, int state); - /* Very specific to the needs of some platforms (h3,h4) - * having calls which can sleep in irda_set_speed. - */ - struct delayed_work gpio_expa; int rx_channel; int tx_channel; unsigned long dest_start; diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/mach/mmc.h index 4435bd4..81d5b36 100644 --- a/arch/arm/plat-omap/include/mach/mmc.h +++ b/arch/arm/plat-omap/include/mach/mmc.h @@ -79,7 +79,6 @@ struct omap_mmc_platform_data { /* use the internal clock */ unsigned internal_clock:1; - s16 power_pin; int switch_pin; /* gpio (card detect) */ int gpio_wp; /* gpio (write protect) */ diff --git a/arch/arm/plat-omap/include/mach/timer-gp.h b/arch/arm/plat-omap/include/mach/timer-gp.h new file mode 100644 index 0000000..c88d346 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/timer-gp.h @@ -0,0 +1,17 @@ +/* + * OMAP2/3 GPTIMER support.headers + * + * Copyright (C) 2009 Nokia Corporation + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H + +int __init omap2_gp_clockevent_set_gptimer(u8 id); + +#endif + diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c index af819bf..abc79d4 100644 --- a/arch/arm/plat-pxa/gpio.c +++ b/arch/arm/plat-pxa/gpio.c @@ -121,6 +121,8 @@ static int __init pxa_init_gpio_chip(int gpio_end) return -ENOMEM; } + memset(chips, 0, nbanks * sizeof(struct pxa_gpio_chip)); + for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { struct gpio_chip *c = &chips[i].chip; @@ -143,6 +145,21 @@ static int __init pxa_init_gpio_chip(int gpio_end) return 0; } +/* Update only those GRERx and GFERx edge detection register bits if those + * bits are set in c->irq_mask + */ +static inline void update_edge_detect(struct pxa_gpio_chip *c) +{ + uint32_t grer, gfer; + + grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask; + gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask; + grer |= c->irq_edge_rise & c->irq_mask; + gfer |= c->irq_edge_fall & c->irq_mask; + __raw_writel(grer, c->regbase + GRER_OFFSET); + __raw_writel(gfer, c->regbase + GFER_OFFSET); +} + static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) { struct pxa_gpio_chip *c; @@ -181,8 +198,7 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) else c->irq_edge_fall &= ~mask; - __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET); - __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET); + update_edge_detect(c); pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), @@ -244,8 +260,7 @@ static void pxa_unmask_muxed_gpio(unsigned int irq) struct pxa_gpio_chip *c = gpio_to_chip(gpio); c->irq_mask |= GPIO_bit(gpio); - __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET); - __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET); + update_edge_detect(c); } static struct irq_chip pxa_muxed_gpio_chip = { |