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| author | Kim Phillips <kim.phillips@freescale.com> | 2006-10-02 20:10:24 -0500 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2006-10-04 15:24:27 +1000 |
| commit | 6c4a2501d0b9fe90882efea5541275a46cda2a1a (patch) | |
| tree | 880f6bc42cb3e56226242184a766947979cc2702 /arch | |
| parent | 7a234d03774a2949d0ce73e3aef56cfdb6856404 (diff) | |
| download | kernel_samsung_tuna-6c4a2501d0b9fe90882efea5541275a46cda2a1a.zip kernel_samsung_tuna-6c4a2501d0b9fe90882efea5541275a46cda2a1a.tar.gz kernel_samsung_tuna-6c4a2501d0b9fe90882efea5541275a46cda2a1a.tar.bz2 | |
[POWERPC] Add initial support for the e300c2 core
Add support for the Freescale e300c2 core found in the MPC832x processor line.
As far as initial kernel support is concerned, the e300c2 core is
identical to the e300c1 found in the mpc834x, except that it's had its
floating point unit chopped off.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/kernel/cputable.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 190a57e..47a613c 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -763,10 +763,10 @@ struct cpu_spec cpu_specs[] = { .cpu_setup = __setup_cpu_603, .platform = "ppc603", }, - { /* e300 (a 603e core, plus some) on 83xx */ + { /* e300c1 (a 603e core, plus some) on 83xx */ .pvr_mask = 0x7fff0000, .pvr_value = 0x00830000, - .cpu_name = "e300", + .cpu_name = "e300c1", .cpu_features = CPU_FTRS_E300, .cpu_user_features = COMMON_USER, .icache_bsize = 32, @@ -774,6 +774,17 @@ struct cpu_spec cpu_specs[] = { .cpu_setup = __setup_cpu_603, .platform = "ppc603", }, + { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */ + .pvr_mask = 0x7fff0000, + .pvr_value = 0x00840000, + .cpu_name = "e300c2", + .cpu_features = CPU_FTRS_E300, + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, + .icache_bsize = 32, + .dcache_bsize = 32, + .cpu_setup = __setup_cpu_603, + .platform = "ppc603", + }, { /* default match, we assume split I/D cache & TB (non-601)... */ .pvr_mask = 0x00000000, .pvr_value = 0x00000000, |