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| author | Colin Cross <ccross@android.com> | 2011-10-15 20:05:17 -0700 |
|---|---|---|
| committer | Colin Cross <ccross@android.com> | 2011-10-15 20:05:17 -0700 |
| commit | a50dfd171ad9d7116163ff4d8d1b8278208aa6c4 (patch) | |
| tree | baf88e705c9965444aeb2984ba07caf53b894581 /arch | |
| parent | 88018d8d877a56e238c726ccd8c22e9b1bf58051 (diff) | |
| download | kernel_samsung_tuna-a50dfd171ad9d7116163ff4d8d1b8278208aa6c4.zip kernel_samsung_tuna-a50dfd171ad9d7116163ff4d8d1b8278208aa6c4.tar.gz kernel_samsung_tuna-a50dfd171ad9d7116163ff4d8d1b8278208aa6c4.tar.bz2 | |
OMAP4+: EMIF: fix ddr self refresh cycles computation
ns_2_cycles uses the global variables T_num and T_den to convert
nanoseconds to cycles, but T_num and T_den are not kept up to date
on every memory bus frequency change. Instead, they are updated only
when a memory frequency is used for the first time.
If ns_2_cycles is called in setup_registers, which runs on every
memory bus frequency change, it will use the memory bus frequency
that was most recently used for the first time. Move the call to
ns_2_cycles into emif_calculate_regs, which is only called the
first time a memory bus frequency is used, and cache the result
for use in setup_registers.
Change-Id: I1db501acee73bcbd738d9fefc65563896ec76585
Signed-off-by: Colin Cross <ccross@android.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/emif.c | 7 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/emif.h | 2 |
2 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/emif.c b/arch/arm/mach-omap2/emif.c index 6d910f2..2144150 100644 --- a/arch/arm/mach-omap2/emif.c +++ b/arch/arm/mach-omap2/emif.c @@ -594,7 +594,7 @@ static void setup_registers(u32 emif_nr, struct emif_regs *regs, u32 volt_state) base + OMAP44XX_EMIF_PWR_MGMT_CTRL_SHDW); /* Configure EMIF Automatic Power Management to Self-refresh mode */ - if (regs->emif_ddr_selfrefresh_time >= 0) { + if (regs->emif_ddr_selfrefresh_cycles >= 0) { u32 num_cycles, ddr_sr_timer; temp = __raw_readl(base + OMAP44XX_EMIF_PWR_MGMT_CTRL_SHDW); @@ -602,7 +602,7 @@ static void setup_registers(u32 emif_nr, struct emif_regs *regs, u32 volt_state) * Configure the self refresh timing * base value starts at 16 cycles mapped to 1( __ffs(16) = 4) */ - num_cycles = ns_2_cycles(regs->emif_ddr_selfrefresh_time); + num_cycles = regs->emif_ddr_selfrefresh_cycles; if (num_cycles >= 16) ddr_sr_timer = __fls(num_cycles) - 3; else @@ -962,7 +962,8 @@ static void emif_calculate_regs(const struct emif_device_details *devices, emif_assert(addressing); regs->RL_final = timings->RL; - regs->emif_ddr_selfrefresh_time = timings->omap_emif_self_refresh_time; + regs->emif_ddr_selfrefresh_cycles = + ns_2_cycles(timings->omap_emif_self_refresh_time); /* * Initial value of EMIF_SDRAM_CONFIG corresponds to the base * frequency - 19.2 MHz diff --git a/arch/arm/mach-omap2/include/mach/emif.h b/arch/arm/mach-omap2/include/mach/emif.h index 3301f98..a29c5e7 100644 --- a/arch/arm/mach-omap2/include/mach/emif.h +++ b/arch/arm/mach-omap2/include/mach/emif.h @@ -277,7 +277,7 @@ struct emif_regs { u32 temp_alert_config_derated; u32 emif_ddr_phy_ctlr_1_init; u32 emif_ddr_phy_ctlr_1_final; - s32 emif_ddr_selfrefresh_time; + s32 emif_ddr_selfrefresh_cycles; }; int omap_emif_setup_registers(u32 freq, |