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| author | Darrick J. Wong <djwong@us.ibm.com> | 2010-06-30 17:45:19 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2010-06-30 22:41:42 -0700 |
| commit | d596043d71ff0d7b3d0bead19b1d68c55f003093 (patch) | |
| tree | 97336d074c772c4ea7715f9fc9114f25fbfab4ea /arch | |
| parent | 980019d74e4b2428362b36a0506519d6d9460800 (diff) | |
| download | kernel_samsung_tuna-d596043d71ff0d7b3d0bead19b1d68c55f003093.zip kernel_samsung_tuna-d596043d71ff0d7b3d0bead19b1d68c55f003093.tar.gz kernel_samsung_tuna-d596043d71ff0d7b3d0bead19b1d68c55f003093.tar.bz2 | |
x86, Calgary: Limit the max PHB number to 256
The x3950 family can have as many as 256 PCI buses in a single system, so
change the limits to the maximum. Since there can only be 256 PCI buses in one
domain, we no longer need the BUG_ON check.
Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
LKML-Reference: <20100701004519.GQ15515@tux1.beaverton.ibm.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/kernel/pci-calgary_64.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c index 0b96b55..078d4ec 100644 --- a/arch/x86/kernel/pci-calgary_64.c +++ b/arch/x86/kernel/pci-calgary_64.c @@ -110,7 +110,7 @@ int use_calgary __read_mostly = 0; * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256 * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128 */ -#define MAX_PHB_BUS_NUM 384 +#define MAX_PHB_BUS_NUM 256 #define PHBS_PER_CALGARY 4 @@ -1056,8 +1056,6 @@ static int __init calgary_init_one(struct pci_dev *dev) struct iommu_table *tbl; int ret; - BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM); - bbar = busno_to_bbar(dev->bus->number); ret = calgary_setup_tar(dev, bbar); if (ret) |