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author | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2009-03-27 12:46:46 +0100 |
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committer | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2009-03-27 12:46:46 +0100 |
commit | 2298169418f43ba5e0919762a4bab95a1227872a (patch) | |
tree | 67cf3133c7bae747ad957c68a650534105a7d8e7 /drivers/ide/pmac.c | |
parent | 130e886708d6e11f3d54e5d27c266578de56f343 (diff) | |
download | kernel_samsung_tuna-2298169418f43ba5e0919762a4bab95a1227872a.zip kernel_samsung_tuna-2298169418f43ba5e0919762a4bab95a1227872a.tar.gz kernel_samsung_tuna-2298169418f43ba5e0919762a4bab95a1227872a.tar.bz2 |
ide: pass command to ide_map_sg()
* Set IDE_TFLAG_WRITE flag and ->rq also for ATA_CMD_PACKET
commands.
* Pass command to ->dma_setup method and update all its
implementations accordingly.
* Pass command instead of request to ide_build_sglist(),
*_build_dmatable() and ide_map_sg().
While at it:
* Fix scc_dma_setup() documentation + use ATA_DMA_WR define.
* Rename sgiioc4_build_dma_table() to sgiioc4_build_dmatable(),
change return value type to 'int' and drop unused 'ddir'
argument.
* Do some minor cleanups in [tx4939]ide_dma_setup().
There should be no functional changes caused by this patch.
Acked-by: Borislav Petkov <petkovbb@gmail.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/pmac.c')
-rw-r--r-- | drivers/ide/pmac.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/drivers/ide/pmac.c b/drivers/ide/pmac.c index f5b85f4c..337d2d5 100644 --- a/drivers/ide/pmac.c +++ b/drivers/ide/pmac.c @@ -404,7 +404,6 @@ kauai_lookup_timing(struct kauai_timing* table, int cycle_time) #define IDE_WAKEUP_DELAY (1*HZ) static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *); -static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq); static void pmac_ide_selectproc(ide_drive_t *drive); static void pmac_ide_kauai_selectproc(ide_drive_t *drive); @@ -1422,8 +1421,7 @@ out: * pmac_ide_build_dmatable builds the DBDMA command list * for a transfer and sets the DBDMA channel to point to it. */ -static int -pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq) +static int pmac_ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd) { ide_hwif_t *hwif = drive->hwif; pmac_ide_hwif_t *pmif = @@ -1431,8 +1429,8 @@ pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq) struct dbdma_cmd *table; volatile struct dbdma_regs __iomem *dma = pmif->dma_regs; struct scatterlist *sg; - int wr = (rq_data_dir(rq) == WRITE); - int i = hwif->cmd.sg_nents, count = 0; + int wr = !!(cmd->tf_flags & IDE_TFLAG_WRITE); + int i = cmd->sg_nents, count = 0; /* DMA table is already aligned */ table = (struct dbdma_cmd *) pmif->dma_table_cpu; @@ -1504,23 +1502,22 @@ use_pio_instead: * Prepare a DMA transfer. We build the DMA table, adjust the timings for * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion */ -static int -pmac_ide_dma_setup(ide_drive_t *drive) +static int pmac_ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) { ide_hwif_t *hwif = drive->hwif; pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); - struct request *rq = hwif->rq; u8 unit = drive->dn & 1, ata4 = (pmif->kind == controller_kl_ata4); + u8 write = !!(cmd->tf_flags & IDE_TFLAG_WRITE); - if (!pmac_ide_build_dmatable(drive, rq)) { - ide_map_sg(drive, rq); + if (pmac_ide_build_dmatable(drive, cmd) == 0) { + ide_map_sg(drive, cmd); return 1; } /* Apple adds 60ns to wrDataSetup on reads */ if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) { - writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0), + writel(pmif->timings[unit] + (write ? 0 : 0x00800000UL), PMAC_IDE_REG(IDE_TIMING_CONFIG)); (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG)); } |