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| author | Grazvydas Ignotas <notasas@gmail.com> | 2010-09-28 16:22:19 +0300 |
|---|---|---|
| committer | Samuel Ortiz <sameo@linux.intel.com> | 2010-10-29 00:30:04 +0200 |
| commit | 8e52e279b241d3a22d52c10a5f934db18b7d0a1b (patch) | |
| tree | 7e90a6286246da448c67b8a016a638b23c485406 /drivers/mfd | |
| parent | a28dbea0ad3bd8144f3348eb5c20fabc2f12b4b5 (diff) | |
| download | kernel_samsung_tuna-8e52e279b241d3a22d52c10a5f934db18b7d0a1b.zip kernel_samsung_tuna-8e52e279b241d3a22d52c10a5f934db18b7d0a1b.tar.gz kernel_samsung_tuna-8e52e279b241d3a22d52c10a5f934db18b7d0a1b.tar.bz2 | |
mfd: Fix TWL4030 COR bit polarity for BCI SIH block
The chip TRM documentation contradicts itself about this bit, page 174
of swcu050e says bit should be 0 for clear-on-read behavior, while
page 487 says it should be 1. Testing shows it should be 1, so set
the .set_cor flag accordingly. This is needed for upcoming BCI
charging driver to function.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd')
| -rw-r--r-- | drivers/mfd/twl4030-irq.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c index b9fda70..381ab26 100644 --- a/drivers/mfd/twl4030-irq.c +++ b/drivers/mfd/twl4030-irq.c @@ -144,6 +144,7 @@ static const struct sih sih_modules_twl4030[6] = { .name = "bci", .module = TWL4030_MODULE_INTERRUPTS, .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, + .set_cor = true, .bits = 12, .bytes_ixr = 2, .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, @@ -408,7 +409,7 @@ static int twl4030_init_sih_modules(unsigned line) * set Clear-On-Read (COR) bit. * * NOTE that sometimes COR polarity is documented as being - * inverted: for MADC and BCI, COR=1 means "clear on write". + * inverted: for MADC, COR=1 means "clear on write". * And for PWR_INT it's not documented... */ if (sih->set_cor) { |