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| author | Colin Cross <ccross@android.com> | 2011-07-12 20:11:00 -0700 |
|---|---|---|
| committer | Colin Cross <ccross@android.com> | 2011-07-12 20:11:00 -0700 |
| commit | 2340c679cabc5477598ee3c9c2044ec8893d42fd (patch) | |
| tree | 2cf2848bea005b9d807710f23dc5519191ca8215 /drivers/mmc/host | |
| parent | 9a489d92af45a7d7c1bba9e0803f73f95d2fd13c (diff) | |
| parent | 620917de59eeb934b9f8cf35cc2d95c1ac8ed0fc (diff) | |
| download | kernel_samsung_tuna-2340c679cabc5477598ee3c9c2044ec8893d42fd.zip kernel_samsung_tuna-2340c679cabc5477598ee3c9c2044ec8893d42fd.tar.gz kernel_samsung_tuna-2340c679cabc5477598ee3c9c2044ec8893d42fd.tar.bz2 | |
Merge commit 'v3.0-rc7' into linux-omap-3.0
Diffstat (limited to 'drivers/mmc/host')
| -rw-r--r-- | drivers/mmc/host/mmci.c | 2 | ||||
| -rw-r--r-- | drivers/mmc/host/mmci.h | 5 |
2 files changed, 6 insertions, 1 deletions
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 7721de9..fe14072 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -582,6 +582,8 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data, data->error = -EILSEQ; } else if (status & MCI_DATATIMEOUT) { data->error = -ETIMEDOUT; + } else if (status & MCI_STARTBITERR) { + data->error = -ECOMM; } else if (status & MCI_TXUNDERRUN) { data->error = -EIO; } else if (status & MCI_RXOVERRUN) { diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index bb32e21..2164e8c 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -86,6 +86,7 @@ #define MCI_CMDRESPEND (1 << 6) #define MCI_CMDSENT (1 << 7) #define MCI_DATAEND (1 << 8) +#define MCI_STARTBITERR (1 << 9) #define MCI_DATABLOCKEND (1 << 10) #define MCI_CMDACTIVE (1 << 11) #define MCI_TXACTIVE (1 << 12) @@ -112,6 +113,7 @@ #define MCI_CMDRESPENDCLR (1 << 6) #define MCI_CMDSENTCLR (1 << 7) #define MCI_DATAENDCLR (1 << 8) +#define MCI_STARTBITERRCLR (1 << 9) #define MCI_DATABLOCKENDCLR (1 << 10) /* Extended status bits for the ST Micro variants */ #define MCI_ST_SDIOITC (1 << 22) @@ -127,6 +129,7 @@ #define MCI_CMDRESPENDMASK (1 << 6) #define MCI_CMDSENTMASK (1 << 7) #define MCI_DATAENDMASK (1 << 8) +#define MCI_STARTBITERRMASK (1 << 9) #define MCI_DATABLOCKENDMASK (1 << 10) #define MCI_CMDACTIVEMASK (1 << 11) #define MCI_TXACTIVEMASK (1 << 12) @@ -150,7 +153,7 @@ #define MCI_IRQENABLE \ (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ - MCI_CMDRESPENDMASK|MCI_CMDSENTMASK) + MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK) /* These interrupts are directed to IRQ1 when two IRQ lines are available */ #define MCI_IRQ1MASK \ |