OMAP4: DPLL cascading: usage of DPLL cascading blocker API on HSI activity

When HSI driver is probed, it sets a constraint to keep HSI Fclk at 96 MHz.
But this constraint was not released, thus it was not possible to enter
OPPLP (used for DPLL cascading).

Now DPLL cascading blocker constraint is set and release based on HSI
activity.

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: Id8ace8f8a4f0a24641e51023346a745ecaaaf423
Signed-off-by: Djamil Elaidi <d-elaidi@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>

1 files changed, 44 insertions, 7 deletions

diff --git a/drivers/omap_hsi/hsi_driver.c b/drivers/omap_hsi/hsi_driver.c
index a2ed3c2..a216c99 100755
--- a/drivers/omap_hsi/hsi_driver.c
+++ b/drivers/omap_hsi/hsi_driver.c
@@ -43,6 +43,17 @@
 #define HSI_RESETDONE_NORMAL_RETRIES	1 /* Reset should complete in 1 R/W */
 					  /* cycle */
 
+#ifdef CONFIG_OMAP4_DPLL_CASCADING
+struct hsi_dpll_cascading_blocker {
+	bool lock_dpll_cascading;
+	struct device *dev;
+	struct work_struct dpll_blocker_work;
+};
+
+static struct hsi_dpll_cascading_blocker dpll_blocker = {
+	.lock_dpll_cascading = true,
+};
+#endif
 
 void hsi_hsr_suspend(struct hsi_dev *hsi_ctrl)
 {
@@ -654,6 +665,22 @@ static int __init hsi_init_gdd_chan_count(struct hsi_dev *hsi_ctrl)
 	return 0;
 }
 
+#ifdef CONFIG_OMAP4_DPLL_CASCADING
+static void hsi_dpll_cascading_blocker_work(struct work_struct *work)
+{
+	struct hsi_dpll_cascading_blocker *dpll_blocker;
+
+	dpll_blocker = container_of(work,
+			struct hsi_dpll_cascading_blocker,
+			dpll_blocker_work);
+
+	if (dpll_blocker->lock_dpll_cascading)
+		omap4_dpll_cascading_blocker_hold(dpll_blocker->dev);
+	else
+		omap4_dpll_cascading_blocker_release(dpll_blocker->dev);
+}
+#endif
+
 /**
 * hsi_clocks_disable_channel - virtual wrapper for disabling HSI clocks for
 * a given channel
@@ -690,10 +717,11 @@ void hsi_clocks_disable_channel(struct device *dev, u8 channel_number,
 	if (hsi_is_hst_controller_busy(hsi_ctrl))
 		dev_dbg(dev, "Disabling clocks with HST FSM not IDLE !\n");
 
-#ifdef K3_0_PORTING_HSI_MISSING_FEATURE
+#ifdef CONFIG_OMAP4_DPLL_CASCADING
 	/* Allow Fclk to change */
-	if (dpll_cascading_blocker_release(dev) < 0)
-		dev_warn(dev, "Error releasing DPLL cascading constraint\n");
+	dpll_blocker.lock_dpll_cascading = false;
+	dpll_blocker.dev = dev;
+	schedule_work(&dpll_blocker.dpll_blocker_work);
 #endif
 
 	pm_runtime_put_sync_suspend(dev);
@@ -731,10 +759,11 @@ int hsi_clocks_enable_channel(struct device *dev, u8 channel_number,
 		return -EEXIST;
 	}
 
-#ifdef K3_0_PORTING_HSI_MISSING_FEATURE
-	/* Prevent Fclk change */
-	if (dpll_cascading_blocker_hold(dev) < 0)
-		dev_warn(dev, "Error holding DPLL cascading constraint\n");
+#ifdef CONFIG_OMAP4_DPLL_CASCADING
+	/* Prevent Fclk to change */
+	dpll_blocker.lock_dpll_cascading = true;
+	dpll_blocker.dev = dev;
+	schedule_work(&dpll_blocker.dpll_blocker_work);
 #endif
 
 	return pm_runtime_get_sync(dev);
@@ -1223,6 +1252,11 @@ static int __init hsi_driver_init(void)
 		goto rback1;
 	}
 
+#ifdef CONFIG_OMAP4_DPLL_CASCADING
+	INIT_WORK(&dpll_blocker.dpll_blocker_work,
+			hsi_dpll_cascading_blocker_work);
+#endif
+
 	/* Register the HSI platform driver */
 	err = platform_driver_probe(&hsi_pdriver, hsi_platform_device_probe);
 	if (err < 0) {
@@ -1240,6 +1274,9 @@ rback1:
 
 static void __exit hsi_driver_exit(void)
 {
+#ifdef CONFIG_OMAP4_DPLL_CASCADING
+	flush_work_sync(&dpll_blocker.dpll_blocker_work);
+#endif
 	platform_driver_unregister(&hsi_pdriver);
 	hsi_debug_exit();
 	hsi_bus_exit();