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| author | Varadarajan, Charulatha <charu@ti.com> | 2012-06-12 21:20:23 +0530 |
|---|---|---|
| committer | Ziyan <jaraidaniel@gmail.com> | 2015-04-17 20:41:14 +0200 |
| commit | c18407a9a170554b7f0da4d7a8d13e51158cd7d3 (patch) | |
| tree | 9498d5ba2db4d8b80fef6643b2a22b768c2c5801 /drivers/video/hdmi_ti_4xxx_ip.c | |
| parent | d161dc1203dc29aa281f17bc36bd52d1b8a1c5c9 (diff) | |
| download | kernel_samsung_tuna-c18407a9a170554b7f0da4d7a8d13e51158cd7d3.zip kernel_samsung_tuna-c18407a9a170554b7f0da4d7a8d13e51158cd7d3.tar.gz kernel_samsung_tuna-c18407a9a170554b7f0da4d7a8d13e51158cd7d3.tar.bz2 | |
OMAP4: HDMI: Fix HDMI_TXPHY_TX_CONTROL.FREQOUT programming
According to TRM, the HDMI_TXPHY_TX_CONTROL.FREQOUT bit has to be programmed
based on the clock frequency. But this bit is always programmed as 1 in the HDMI
driver irrespective of the clock frequency values. Fix this and program
HDMI_TXPHY_TX_CONTROL.FREQOUT based on the clock frequency.
Change-Id: I25a4c335ec773e241cc0daca5c1c1c8f223cd4a0
Signed-off-by: TAKAHASHI, Masato <m_takahashi@ti.com>
Signed-off-by: Varadarajan, Charulatha <charu@ti.com>
Diffstat (limited to 'drivers/video/hdmi_ti_4xxx_ip.c')
| -rw-r--r-- | drivers/video/hdmi_ti_4xxx_ip.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/video/hdmi_ti_4xxx_ip.c b/drivers/video/hdmi_ti_4xxx_ip.c index fdb9b7b..d5a90a9 100644 --- a/drivers/video/hdmi_ti_4xxx_ip.c +++ b/drivers/video/hdmi_ti_4xxx_ip.c @@ -407,7 +407,7 @@ int hdmi_ti_4xxx_pll_program(struct hdmi_ip_data *ip_data, return 0; } -int hdmi_ti_4xxx_phy_init(struct hdmi_ip_data *ip_data) +int hdmi_ti_4xxx_phy_init(struct hdmi_ip_data *ip_data, int phy) { u16 r = 0; @@ -430,7 +430,15 @@ int hdmi_ti_4xxx_phy_init(struct hdmi_ip_data *ip_data) * Write to phy address 0 to configure the clock * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field */ - REG_FLD_MOD(hdmi_phy_base(ip_data), HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); + if (phy <= 50000) + REG_FLD_MOD(hdmi_phy_base(ip_data), HDMI_TXPHY_TX_CTRL, 0x0, 31, + 30); + else if ((50000 < phy) && (phy <= 100000)) + REG_FLD_MOD(hdmi_phy_base(ip_data), HDMI_TXPHY_TX_CTRL, 0x1, 31, + 30); + else + REG_FLD_MOD(hdmi_phy_base(ip_data), HDMI_TXPHY_TX_CTRL, 0x2, 31, + 30); /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ hdmi_write_reg(hdmi_phy_base(ip_data), |