diff options
| author | Michael Chan <mchan@broadcom.com> | 2007-06-04 21:17:10 -0700 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2007-06-07 13:38:36 -0700 |
| commit | 7947b20ebae785ba25154aa1a9a00a98a22de75a (patch) | |
| tree | 6e9076d1d28c3ba12f5483a56129d6bd812fe240 /drivers | |
| parent | 7244d545c123ff33a3a5bff7fcb96a07778c32d1 (diff) | |
| download | kernel_samsung_tuna-7947b20ebae785ba25154aa1a9a00a98a22de75a.zip kernel_samsung_tuna-7947b20ebae785ba25154aa1a9a00a98a22de75a.tar.gz kernel_samsung_tuna-7947b20ebae785ba25154aa1a9a00a98a22de75a.tar.bz2 | |
[BNX2]: Fix netdev watchdog on 5708.
There's a bug in the driver that only initializes half of the context
memory on the 5708. Surprisingly, this works most of the time except
for some occasional netdev watchdogs when sending a lot of 64-byte
packets. The fix is to add the missing code to initialize the 2nd
halves of all context memory.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Acked-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/bnx2.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index da7c3b0..9789f05 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c @@ -1811,6 +1811,7 @@ bnx2_init_context(struct bnx2 *bp) vcid = 96; while (vcid) { u32 vcid_addr, pcid_addr, offset; + int i; vcid--; @@ -1831,16 +1832,20 @@ bnx2_init_context(struct bnx2 *bp) pcid_addr = vcid_addr; } - REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00); - REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); + for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) { + vcid_addr += (i << PHY_CTX_SHIFT); + pcid_addr += (i << PHY_CTX_SHIFT); - /* Zero out the context. */ - for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) { - CTX_WR(bp, 0x00, offset, 0); - } + REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00); + REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); - REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); - REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); + /* Zero out the context. */ + for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) + CTX_WR(bp, 0x00, offset, 0); + + REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); + REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); + } } } |