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author | Kyle McMartin <kyle@mcmartin.ca> | 2008-07-28 23:02:13 -0400 |
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committer | Kyle McMartin <kyle@hera.kernel.org> | 2008-10-10 16:32:29 +0000 |
commit | deae26bf6a10e47983606f5df080b91e97650ead (patch) | |
tree | 84a8a68145d0f713d7c5a1f9e6b3b03be9b3a4c8 /include/asm-parisc/cache.h | |
parent | 6c86cb8237bf08443806089130dc108051569a93 (diff) | |
download | kernel_samsung_tuna-deae26bf6a10e47983606f5df080b91e97650ead.zip kernel_samsung_tuna-deae26bf6a10e47983606f5df080b91e97650ead.tar.gz kernel_samsung_tuna-deae26bf6a10e47983606f5df080b91e97650ead.tar.bz2 |
parisc: move include/asm-parisc to arch/parisc/include/asm
Diffstat (limited to 'include/asm-parisc/cache.h')
-rw-r--r-- | include/asm-parisc/cache.h | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/include/asm-parisc/cache.h b/include/asm-parisc/cache.h deleted file mode 100644 index 32c2cca..0000000 --- a/include/asm-parisc/cache.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * include/asm-parisc/cache.h - */ - -#ifndef __ARCH_PARISC_CACHE_H -#define __ARCH_PARISC_CACHE_H - - -/* - * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have - * 32-byte cachelines. The default configuration is not for SMP anyway, - * so if you're building for SMP, you should select the appropriate - * processor type. There is a potential livelock danger when running - * a machine with this value set too small, but it's more probable you'll - * just ruin performance. - */ -#ifdef CONFIG_PA20 -#define L1_CACHE_BYTES 64 -#define L1_CACHE_SHIFT 6 -#else -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 -#endif - -#ifndef __ASSEMBLY__ - -#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) - -#define SMP_CACHE_BYTES L1_CACHE_BYTES - -#define __read_mostly __attribute__((__section__(".data.read_mostly"))) - -void parisc_cache_init(void); /* initializes cache-flushing */ -void disable_sr_hashing_asm(int); /* low level support for above */ -void disable_sr_hashing(void); /* turns off space register hashing */ -void free_sid(unsigned long); -unsigned long alloc_sid(void); - -struct seq_file; -extern void show_cache_info(struct seq_file *m); - -extern int split_tlb; -extern int dcache_stride; -extern int icache_stride; -extern struct pdc_cache_info cache_info; -void parisc_setup_cache_timing(void); - -#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr)); -#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr)); -#define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr)); - -#endif /* ! __ASSEMBLY__ */ - -/* Classes of processor wrt: disabling space register hashing */ - -#define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */ -#define SRHASH_PCXL 1 /* pcxl */ -#define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */ - -#endif |