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| author | Larry Finger <Larry.Finger@lwfinger.net> | 2008-08-19 12:50:31 -0500 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2008-08-29 16:24:05 -0400 |
| commit | 095f695cbb07281682462da0618fffabb499d0be (patch) | |
| tree | b46e86b862d0c5928cc1829f22ebef1b57ecfc14 /include/linux/ssb | |
| parent | 2f58bbf27fe5321a7a208be9071efc54e8a8a3bd (diff) | |
| download | kernel_samsung_tuna-095f695cbb07281682462da0618fffabb499d0be.zip kernel_samsung_tuna-095f695cbb07281682462da0618fffabb499d0be.tar.gz kernel_samsung_tuna-095f695cbb07281682462da0618fffabb499d0be.tar.bz2 | |
ssb: Update for Rev. 5 SPROM
Although a revision 5 SPROM has not been seen in the wild, the
open-source portion of the MIPS driver 4.150.10.5 describes its
layout, which is mostly inherited from revision 4. This patch
implements the differences.
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Acked-by: Michael Buesch <mb@bu3sch.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include/linux/ssb')
| -rw-r--r-- | include/linux/ssb/ssb_regs.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h index ebad0ba..271bb4b 100644 --- a/include/linux/ssb/ssb_regs.h +++ b/include/linux/ssb/ssb_regs.h @@ -316,6 +316,21 @@ #define SSB_SPROM4_PA1B1 0x1090 #define SSB_SPROM4_PA1B2 0x1092 +/* SPROM Revision 5 (inherits most data from rev 4) */ +#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */ +#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */ +#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */ +#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */ +#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */ +#define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */ +#define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */ +#define SSB_SPROM5_GPIOA_P1_SHIFT 8 +#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */ +#define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */ +#define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */ +#define SSB_SPROM5_GPIOB_P3_SHIFT 8 + + /* Values for SSB_SPROM1_BINF_CCODE */ enum { SSB_SPROM1CCODE_WORLD = 0, |