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| author | Matt Carlson <mcarlson@broadcom.com> | 2007-10-07 23:27:28 -0700 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2007-10-10 16:54:44 -0700 |
| commit | 9974a356b204833b32173210ca25edfdc24dcdd5 (patch) | |
| tree | 1b6a4d69ec46c01934fb5ff2cf4d76d57a103752 /include | |
| parent | 8658251dc3fed54b09991a2c5e0a7084755157d7 (diff) | |
| download | kernel_samsung_tuna-9974a356b204833b32173210ca25edfdc24dcdd5.zip kernel_samsung_tuna-9974a356b204833b32173210ca25edfdc24dcdd5.tar.gz kernel_samsung_tuna-9974a356b204833b32173210ca25edfdc24dcdd5.tar.bz2 | |
[TG3]: Walk PCI capability lists.
Newer tg3 devices shuffle around the registers in PCI configuration
space. This patch changes the way the driver accesses the PCI
capabilities registers. Hardcoded register locations are replaced with
offsets from pci_find_capability() return values.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/pci_regs.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 495d368..423d592 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -316,7 +316,20 @@ #define PCI_X_CMD 2 /* Modes & Features */ #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */ +#define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */ +#define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */ +#define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */ #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ + /* Max # of outstanding split transactions */ +#define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */ +#define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */ +#define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */ +#define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */ +#define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */ +#define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */ +#define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ +#define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ #define PCI_X_STATUS 4 /* PCI-X capabilities */ |