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| author | Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> | 2011-07-14 09:52:38 +0900 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-04-22 16:21:44 -0700 |
| commit | c9f52d613590b10630ab8bb222ae05c551389425 (patch) | |
| tree | 25df3b9290a78665e9d9e1edab7bae2e12061da2 /mm/memory-failure.c | |
| parent | 724d7ad550fb6ed11ce40425eb0206f90faf665a (diff) | |
| download | kernel_samsung_tuna-c9f52d613590b10630ab8bb222ae05c551389425.zip kernel_samsung_tuna-c9f52d613590b10630ab8bb222ae05c551389425.tar.gz kernel_samsung_tuna-c9f52d613590b10630ab8bb222ae05c551389425.tar.bz2 | |
pch_dma: Fix CTL register access issue
commit 0b052f4a088ddc47a5da23dd733522241314cfb4 upstream.
Currently, Mode-Control register is accessed by read-modify-write.
According to DMA hardware specifications datasheet, prohibits this method.
Because this register resets to 0 by DMA HW after DMA transfer completes.
Thus, current read-modify-write processing can cause unexpected behavior.
The datasheet says in case of writing Mode-Control register, set the value for only target channel, the others must set '11b'.
e.g. Set DMA0=01b DMA11=10b
CTL0=33333331h
CTL2=00002333h
NOTE:
CTL0 includes DMA0~7 Mode-Control register.
CTL2 includes DMA8~11 Mode-Control register.
This patch modifies the issue.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'mm/memory-failure.c')
0 files changed, 0 insertions, 0 deletions