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author | Misael Lopez Cruz <misael.lopez@ti.com> | 2011-11-15 00:47:10 -0600 |
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committer | Simon Wilson <simonwilson@google.com> | 2012-02-01 17:32:45 -0800 |
commit | 9e95bb9ec2e1b5e19c68ee143fb317fdd92f1505 (patch) | |
tree | 3dd6fff092e78654808a7231cd487a99284eb99d /sound/soc/omap | |
parent | dfe2d235d0369b2c8cd45395596f7b2283d932f1 (diff) | |
download | kernel_samsung_tuna-9e95bb9ec2e1b5e19c68ee143fb317fdd92f1505.zip kernel_samsung_tuna-9e95bb9ec2e1b5e19c68ee143fb317fdd92f1505.tar.gz kernel_samsung_tuna-9e95bb9ec2e1b5e19c68ee143fb317fdd92f1505.tar.bz2 |
ASoC: omap-mcasp: Relax S/PDIF clocks/frame constraint
The first step in the current McASP clock dividers calculation is
very strict with respect to the McASP FCLK being an integer multiple
of 128 (number of clocks required for each S/PDIF frame).
The clock divider calculation algorithm doesn't search for exact
matches, but for dividers which can produce clock drift within an
allowed PPM range. For this reason, rejecting McASP FCLK rates not
divisible by 128, reduces the space of rates the algorithm can work
on. By simply including the clocks per frame value in divider
calculation we give more flexibility to the algorithm.
Change-Id: Ic007f9fa9e776c2e5475a36b5444e2ec39c8b0bb
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Diffstat (limited to 'sound/soc/omap')
-rw-r--r-- | sound/soc/omap/omap-mcasp.c | 14 |
1 files changed, 3 insertions, 11 deletions
diff --git a/sound/soc/omap/omap-mcasp.c b/sound/soc/omap/omap-mcasp.c index b7713a2..e0a6e24 100644 --- a/sound/soc/omap/omap-mcasp.c +++ b/sound/soc/omap/omap-mcasp.c @@ -289,20 +289,12 @@ static int mcasp_compute_clock_dividers(long fclk_rate, int tgt_sample_rate, BUG_ON(!out_div_lo); BUG_ON(!out_div_hi); - /* Start by making sure the fclk is divisible by 128 (the number of - * clocks present in a single S/PDIF frame. - */ - if (fclk_rate & 0x7F) - return -EINVAL; - - fclk_rate >>= 7; - - /* rounded division: fclk_rate / tgt_sample_rate + 0.5 */ - divisor = (2 * fclk_rate + tgt_sample_rate) / (2 * tgt_sample_rate); + /* A single S/PDIF frame requires 128 clocks */ + divisor = DIV_ROUND_CLOSEST(fclk_rate, tgt_sample_rate << 7); if (!divisor) return -EINVAL; - sample_rate = fclk_rate / divisor; + sample_rate = (fclk_rate >> 7) / divisor; /* ppm calculation in two steps to avoid overflow */ ppm = abs(tgt_sample_rate - sample_rate); |