diff options
| -rwxr-xr-x | arch/arm/mach-omap2/emif.c | 15 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/emif.h | 1 | ||||
| -rwxr-xr-x | arch/arm/mach-omap2/lpddr2_elpida_data.c | 2 | ||||
| -rwxr-xr-x | arch/arm/mach-omap2/pm44xx.c | 40 |
4 files changed, 54 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/emif.c b/arch/arm/mach-omap2/emif.c index 83b7f83..e951167 100755 --- a/arch/arm/mach-omap2/emif.c +++ b/arch/arm/mach-omap2/emif.c @@ -534,8 +534,10 @@ static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS; else if (freq <= 200000000) val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ; - else + else if (freq <= 400000000) val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ; + else + val = EMIF_DLL_SLAVE_DLY_CTRL_466_MHZ; mask_n_set(phy, OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT, OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK, val); @@ -660,6 +662,17 @@ static void setup_registers(u32 emif_nr, struct emif_regs *regs, u32 volt_state) mask_n_set(temp, OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT, OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK, regs->emif_ddr_phy_ctlr_1_final); + + /* + * Set Read Latency value RL=0xB according to OMAP4470 LPDDR + * interface configuration update for 466 MHz + */ + if (regs->freq == 466666666) { + mask_n_set(temp, OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT, + OMAP44XX_REG_READ_LATENCY_SHDW_MASK, + regs->RL_final); + } + __raw_writel(temp, base + OMAP44XX_EMIF_DDR_PHY_CTRL_1_SHDW); __raw_writel(regs->temp_alert_config, diff --git a/arch/arm/mach-omap2/include/mach/emif.h b/arch/arm/mach-omap2/include/mach/emif.h index f257241..18614c3 100644 --- a/arch/arm/mach-omap2/include/mach/emif.h +++ b/arch/arm/mach-omap2/include/mach/emif.h @@ -173,6 +173,7 @@ * values suggested by hw team. */ #define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF +#define EMIF_DLL_SLAVE_DLY_CTRL_466_MHZ 0x37 #define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 #define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 #define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF diff --git a/arch/arm/mach-omap2/lpddr2_elpida_data.c b/arch/arm/mach-omap2/lpddr2_elpida_data.c index a4148f9..ecfad06 100755 --- a/arch/arm/mach-omap2/lpddr2_elpida_data.c +++ b/arch/arm/mach-omap2/lpddr2_elpida_data.c @@ -16,7 +16,7 @@ const struct lpddr2_timings lpddr2_elpida_timings_466_mhz = { .max_freq = 466666666, - .RL = 7, + .RL = 11, .tRPab = 21, .tRCD = 18, .tWR = 13, diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index 065a94f..74c7255 100755 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -1126,6 +1126,37 @@ static u32 __init _usec_to_val_scrm(unsigned long rate, u32 usec, } +/* + * According to the OMAP4470 LPDDR interface configuration + * update for 466MHz Slew Rate should be set to “FASTEST” + * and Impedance Control to “Drv12”: + * - CONTROL_LPDDR2IOx_2[LPDDR2IO1_GR10_SR] = 0 + * - CONTROL_LPDDR2IOx_2[LPDDR2IO1_GR10_I] = 7 + * where x=[1-2] + */ +static void __init syscontrol_lpddr2io_config_update_466_mhz(void) +{ + u32 v; + + pr_info("OMAP4470 LPDDR interface configuration update for 466 MHz\n"); + + /* Setup LPDDR2IO1_2 */ + v = omap4_ctrl_pad_readl( + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2); + v &= ~OMAP4_LPDDR2IO1_GR10_SR_MASK; + v |= OMAP4_LPDDR2IO1_GR10_I_MASK; + omap4_ctrl_pad_writel(v, + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2); + + /* Setup LPDDR2IO2_2 */ + v = omap4_ctrl_pad_readl( + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2); + v &= ~OMAP4_LPDDR2IO2_GR10_SR_MASK; + v |= OMAP4_LPDDR2IO2_GR10_I_MASK; + omap4_ctrl_pad_writel(v, + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2); +} + static void __init syscontrol_setup_regs(void) { u32 v; @@ -1134,14 +1165,19 @@ static void __init syscontrol_setup_regs(void) v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3); v &= ~(OMAP4_LPDDR21_VREF_EN_CA_MASK | OMAP4_LPDDR21_VREF_EN_DQ_MASK); v |= OMAP4_LPDDR21_VREF_AUTO_EN_CA_MASK | OMAP4_LPDDR21_VREF_AUTO_EN_DQ_MASK; - omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3); + omap4_ctrl_pad_writel(v, + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3); v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3); v &= ~(OMAP4_LPDDR21_VREF_EN_CA_MASK | OMAP4_LPDDR21_VREF_EN_DQ_MASK); v |= OMAP4_LPDDR21_VREF_AUTO_EN_CA_MASK | OMAP4_LPDDR21_VREF_AUTO_EN_DQ_MASK; - omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3); + omap4_ctrl_pad_writel(v, + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3); syscontrol_lpddr_clk_io_errata(true); + + if (cpu_is_omap447x()) + syscontrol_lpddr2io_config_update_466_mhz(); } static void __init prcm_setup_regs(void) |