diff options
| -rw-r--r-- | arch/arm/mach-omap2/dpll44xx.c | 7 | ||||
| -rwxr-xr-x[-rw-r--r--] | drivers/cpufreq/cpufreq_interactive.c | 20 | ||||
| -rw-r--r-- | include/linux/cpufreq.h | 5 |
3 files changed, 31 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 36ccfec..cd22c0d 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -19,6 +19,7 @@ #ifdef CONFIG_OMAP4_DPLL_CASCADING #include <linux/console.h> #include <linux/slab.h> +#include <linux/cpufreq.h> #include "dvfs.h" #include "smartreflex.h" #endif @@ -1532,8 +1533,8 @@ int omap4_dpll_cascading_blocker_hold(struct device *dev) /* exit point of DPLL cascading */ ret = omap4_dpll_low_power_cascade_exit(); + cpufreq_interactive_set_timer_rate(200 * USEC_PER_MSEC, 1); } - out: mutex_unlock(&omap_dvfs_lock); console_unlock(); @@ -1588,8 +1589,12 @@ int omap4_dpll_cascading_blocker_release(struct device *dev) && !omap4_is_in_dpll_cascading() && omap4_abe_can_enter_dpll_cascading()) { + cpufreq_interactive_set_timer_rate(200 * USEC_PER_MSEC, 0); /* enter point of DPLL cascading */ ret = omap4_dpll_low_power_cascade_enter(); + if (ret) + cpufreq_interactive_set_timer_rate( + 200 * USEC_PER_MSEC, 1); } out: mutex_unlock(&omap_dvfs_lock); diff --git a/drivers/cpufreq/cpufreq_interactive.c b/drivers/cpufreq/cpufreq_interactive.c index 7d1952c..15f6724 100644..100755 --- a/drivers/cpufreq/cpufreq_interactive.c +++ b/drivers/cpufreq/cpufreq_interactive.c @@ -87,6 +87,9 @@ static unsigned long min_sample_time = DEFAULT_MIN_SAMPLE_TIME; */ #define DEFAULT_TIMER_RATE (20 * USEC_PER_MSEC) static unsigned long timer_rate = DEFAULT_TIMER_RATE; +#ifdef CONFIG_OMAP4_DPLL_CASCADING +static unsigned long default_timer_rate; +#endif /* * Wait this long before raising speed above hispeed, by default a single @@ -122,6 +125,19 @@ struct cpufreq_governor cpufreq_gov_interactive = { .owner = THIS_MODULE, }; +#ifdef CONFIG_OMAP4_DPLL_CASCADING +void cpufreq_interactive_set_timer_rate(unsigned long val, unsigned int reset) +{ + if (!reset) { + default_timer_rate = timer_rate; + timer_rate = val; + } else { + if (timer_rate == val) + timer_rate = default_timer_rate; + } +} +#endif + static void cpufreq_interactive_timer_resched( struct cpufreq_interactive_cpuinfo *pcpu) { @@ -1014,6 +1030,10 @@ static int __init cpufreq_interactive_init(void) unsigned int i; struct cpufreq_interactive_cpuinfo *pcpu; struct sched_param param = { .sched_priority = MAX_RT_PRIO-1 }; + +#ifdef CONFIG_OMAP4_DPLL_CASCADING + default_timer_rate = DEFAULT_TIMER_RATE; +#endif /* Initalize per-cpu timers */ for_each_possible_cpu(i) { diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 905ea72..08f72c2 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -331,6 +331,11 @@ static inline unsigned int cpufreq_quick_get(unsigned int cpu) } #endif +#if defined(CONFIG_CPU_FREQ_GOV_INTERACTIVE) && \ + defined(CONFIG_OMAP4_DPLL_CASCADING) +extern void cpufreq_interactive_set_timer_rate(unsigned long val, + unsigned int reset); +#endif /********************************************************************* * CPUFREQ DEFAULT GOVERNOR * |