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-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c175
-rwxr-xr-xarch/arm/mach-omap2/opp4xxx_data.c60
-rw-r--r--arch/arm/mach-omap2/pm.c2
3 files changed, 206 insertions, 31 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 137e816..7e000d0 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -45,6 +45,10 @@
static int omap4_virt_l3_set_rate(struct clk *clk, unsigned long rate);
static long omap4_virt_l3_round_rate(struct clk *clk, unsigned long rate);
static unsigned long omap4_virt_l3_recalc(struct clk *clk);
+static int omap4_virt_iva_set_rate(struct clk *clk, unsigned long rate);
+static long omap4_virt_iva_round_rate(struct clk *clk, unsigned long rate);
+static int omap4_virt_dsp_set_rate(struct clk *clk, unsigned long rate);
+static long omap4_virt_dsp_round_rate(struct clk *clk, unsigned long rate);
/* Root clocks */
static struct clk extalt_clkin_ck = {
@@ -763,6 +767,22 @@ static struct clk dpll_iva_m5x2_ck = {
.set_rate = &omap2_clksel_set_rate,
};
+static struct clk virt_iva_ck = {
+ .name = "virt_iva_ck",
+ .parent = &dpll_iva_m5x2_ck,
+ .ops = &clkops_null,
+ .round_rate = &omap4_virt_iva_round_rate,
+ .set_rate = &omap4_virt_iva_set_rate,
+};
+
+static struct clk virt_dsp_ck = {
+ .name = "virt_dsp_ck",
+ .parent = &dpll_iva_m4x2_ck,
+ .ops = &clkops_null,
+ .round_rate = &omap4_virt_dsp_round_rate,
+ .set_rate = &omap4_virt_dsp_set_rate,
+};
+
/* DPLL_MPU */
static struct dpll_data dpll_mpu_dd = {
.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
@@ -3527,6 +3547,8 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_44XX),
CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_44XX),
CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_44XX),
+ CLK(NULL, "virt_iva_ck", &virt_iva_ck, CK_44XX),
+ CLK(NULL, "virt_dsp_ck", &virt_dsp_ck, CK_44XX),
CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_44XX),
CLK(NULL, "virt_dpll_mpu_ck", &virt_dpll_mpu_ck, (CK_446X | CK_447X)),
CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_44XX),
@@ -3885,6 +3907,159 @@ static int omap4_virt_l3_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
+#define DPLL_IVA_M4_OPP50_RATE 232800000
+#define DPLL_IVA_M4_OPP100_RATE 465500000
+#define DPLL_IVA_M4_OPPTURBO_RATE 496000000
+#define DPLL_IVA_M4_OPPNITRO_RATE 430000000
+#define DPLL_IVA_M4_OPPNITROSB_RATE 500000000
+
+#define DPLL_IVA_M5_OPP50_RATE 133100000
+#define DPLL_IVA_M5_OPP100_RATE 266000000
+#define DPLL_IVA_M5_OPPTURBO_RATE 331000000
+#define DPLL_IVA_M5_OPPNITRO_RATE 430000000
+#define DPLL_IVA_M5_OPPNITROSB_RATE 500000000
+
+#define DPLL_IVA_OPP50_RATE 1862400000
+#define DPLL_IVA_OPP100_RATE 1862400000
+#define DPLL_IVA_OPPTURBO_RATE 992000000
+#define DPLL_IVA_OPPNITRO_RATE 1290000000
+#define DPLL_IVA_OPPNITROSB_RATE 1500000000
+
+struct virt_iva_ck_deps {
+ unsigned long iva_ck_rate;
+ unsigned long dsp_ck_rate;
+ unsigned long iva_dpll_rate;
+};
+
+static struct virt_iva_ck_deps omap4_virt_iva_clk_deps[] = {
+ { /* OPP 50 */
+ .iva_ck_rate = DPLL_IVA_M5_OPP50_RATE,
+ .dsp_ck_rate = DPLL_IVA_M4_OPP50_RATE,
+ .iva_dpll_rate = DPLL_IVA_OPP50_RATE,
+ },
+ { /* OPP 100 */
+ .iva_ck_rate = DPLL_IVA_M5_OPP100_RATE,
+ .dsp_ck_rate = DPLL_IVA_M4_OPP100_RATE,
+ .iva_dpll_rate = DPLL_IVA_OPP100_RATE,
+ },
+ { /* OPP TURBO */
+ .iva_ck_rate = DPLL_IVA_M5_OPPTURBO_RATE,
+ .dsp_ck_rate = DPLL_IVA_M4_OPPTURBO_RATE,
+ .iva_dpll_rate = DPLL_IVA_OPPTURBO_RATE,
+ },
+ { /* OPP NITRO */
+ .iva_ck_rate = DPLL_IVA_M5_OPPNITRO_RATE,
+ .dsp_ck_rate = DPLL_IVA_M4_OPPNITRO_RATE,
+ .iva_dpll_rate = DPLL_IVA_OPPNITRO_RATE,
+ },
+ { /* OPP NITROSB */
+ .iva_ck_rate = DPLL_IVA_M5_OPPNITROSB_RATE,
+ .dsp_ck_rate = DPLL_IVA_M4_OPPNITROSB_RATE,
+ .iva_dpll_rate = DPLL_IVA_OPPNITROSB_RATE,
+ },
+};
+
+static long omap4_virt_iva_round_rate(struct clk *clk, unsigned long rate)
+{
+ struct virt_iva_ck_deps *iva_deps = NULL;
+ long last_diff = LONG_MAX;
+ int i;
+
+ if (!clk)
+ return 0;
+
+ for (i = 0; i < ARRAY_SIZE(omap4_virt_iva_clk_deps); i++) {
+ long diff;
+ iva_deps = &omap4_virt_iva_clk_deps[i];
+ diff = abs(rate - iva_deps->iva_ck_rate);
+ if (diff >= last_diff) {
+ iva_deps = &omap4_virt_iva_clk_deps[i-1];
+ break;
+ }
+ last_diff = diff;
+ }
+
+ if (!iva_deps)
+ return 0;
+
+ return iva_deps->iva_ck_rate;
+}
+
+static int omap4_virt_iva_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct virt_iva_ck_deps *iva_deps = NULL;
+ long next_iva_dpll_rate;
+ int i, ret = 0;
+ struct clk *iva_ck = &dpll_iva_m5x2_ck;
+ struct clk *dsp_ck = &dpll_iva_m4x2_ck;
+ struct clk *dpll_ck = &dpll_iva_ck;
+
+ if (!clk)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(omap4_virt_iva_clk_deps); i++)
+ if (rate == omap4_virt_iva_clk_deps[i].iva_ck_rate)
+ break;
+
+ if (i < ARRAY_SIZE(omap4_virt_iva_clk_deps))
+ iva_deps = &omap4_virt_iva_clk_deps[i];
+ else
+ return -EINVAL;
+
+ next_iva_dpll_rate = dpll_ck->round_rate(dpll_ck,
+ iva_deps->iva_dpll_rate / 2);
+
+ if (next_iva_dpll_rate == dpll_ck->rate)
+ goto set_clock_rates;
+ else if (next_iva_dpll_rate < dpll_ck->rate)
+ goto set_dpll_rate;
+
+ if (iva_deps->iva_ck_rate < iva_ck->rate) {
+ ret = omap4_clksel_set_rate(iva_ck, iva_deps->iva_ck_rate);
+ if (ret)
+ goto out;
+ }
+
+ if (iva_deps->dsp_ck_rate < dsp_ck->rate) {
+ ret = omap4_clksel_set_rate(dsp_ck, iva_deps->dsp_ck_rate);
+ if (ret)
+ goto out;
+ }
+
+set_dpll_rate:
+ ret = dpll_ck->set_rate(dpll_ck, next_iva_dpll_rate);
+ if (ret)
+ goto out;
+
+ propagate_rate(dpll_ck);
+
+set_clock_rates:
+ ret = omap4_clksel_set_rate(iva_ck, iva_deps->iva_ck_rate);
+ if (ret)
+ goto out;
+
+ ret = omap4_clksel_set_rate(dsp_ck, iva_deps->dsp_ck_rate);
+ if (ret)
+ goto out;
+
+ clk->rate = iva_deps->iva_ck_rate;
+ return 0;
+
+out:
+ return ret;
+};
+
+static long omap4_virt_dsp_round_rate(struct clk *clk, unsigned long rate)
+{
+ return rate;
+};
+
+static int omap4_virt_dsp_set_rate(struct clk *clk, unsigned long rate)
+{
+ clk->rate = rate;
+ return 0;
+};
+
int __init omap4xxx_clk_init(void)
{
struct omap_clk *c;
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index 6578a99..2fe107f 100755
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -129,11 +129,11 @@ static struct omap_opp_def __initdata omap443x_opp_def_list[] = {
/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
OPP_INITIALIZER("l3_main_1", "virt_l3_ck", "core", true, 200000000, OMAP4430_VDD_CORE_OPP100_UV),
/* IVA OPP1 - OPP50 */
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 133000000, OMAP4430_VDD_IVA_OPP50_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", true, 133000000, OMAP4430_VDD_IVA_OPP50_UV),
/* IVA OPP2 - OPP100 */
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 266100000, OMAP4430_VDD_IVA_OPP100_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", true, 266100000, OMAP4430_VDD_IVA_OPP100_UV),
/* IVA OPP3 - OPP-Turbo */
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 332000000, OMAP4430_VDD_IVA_OPPTURBO_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", false, 332000000, OMAP4430_VDD_IVA_OPPTURBO_UV),
/* SGX OPP1 - OPP50 */
OPP_INITIALIZER("gpu", "dpll_per_m7x2_ck", "core", true, 153600000, OMAP4430_VDD_CORE_OPP50_UV),
/* SGX OPP2 - OPP100 */
@@ -145,11 +145,11 @@ static struct omap_opp_def __initdata omap443x_opp_def_list[] = {
/* FDIF OPP3 - OPP100 */
OPP_INITIALIZER("fdif", "fdif_fck", "core", true, 128000000, OMAP4430_VDD_CORE_OPP100_UV),
/* DSP OPP1 - OPP50 */
- OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", true, 232750000, OMAP4430_VDD_IVA_OPP50_UV),
+ OPP_INITIALIZER("dsp_c0", "virt_dsp_ck", "iva", true, 232750000, OMAP4430_VDD_IVA_OPP50_UV),
/* DSP OPP2 - OPP100 */
- OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", true, 465500000, OMAP4430_VDD_IVA_OPP100_UV),
+ OPP_INITIALIZER("dsp_c0", "virt_dsp_ck", "iva", true, 465500000, OMAP4430_VDD_IVA_OPP100_UV),
/* DSP OPP3 - OPPTB */
- OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", false, 496000000, OMAP4430_VDD_IVA_OPPTURBO_UV),
+ OPP_INITIALIZER("dsp_c0", "virt_dsp_ck", "iva", false, 496000000, OMAP4430_VDD_IVA_OPPTURBO_UV),
/* HSI OPP1 - OPP50 */
OPP_INITIALIZER("hsi", "hsi_fck", "core", true, 96000000, OMAP4430_VDD_CORE_OPP50_UV),
/* HSI OPP2 - OPP100 */
@@ -251,20 +251,20 @@ static struct omap_opp_def __initdata omap446x_opp_def_list[] = {
OPP_INITIALIZER("l3_main_1", "virt_l3_ck", "core", true, 200000000, OMAP4460_VDD_CORE_OPP100_UV),
OPP_INITIALIZER("l3_main_1", "virt_l3_ck", "core", true, 200000000, OMAP4460_VDD_CORE_OPP100_OV_UV),
/* IVA OPP1 - OPP50 */
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 133000000, OMAP4460_VDD_IVA_OPP50_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", true, 133000000, OMAP4460_VDD_IVA_OPP50_UV),
/* IVA OPP2 - OPP100 */
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 266100000, OMAP4460_VDD_IVA_OPP100_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", true, 266100000, OMAP4460_VDD_IVA_OPP100_UV),
/*
* IVA OPP3 - OPP-Turbo + Disabled as the reference schematics
* recommends Phoenix VCORE2 which can supply only 600mA - so the ones
* above this OPP frequency, even though OMAP is capable, should be
* enabled by board file which is sure of the chip power capability
*/
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 332000000, OMAP4460_VDD_IVA_OPPTURBO_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", false, 332000000, OMAP4460_VDD_IVA_OPPTURBO_UV),
/* IVA OPP4 - OPP-Nitro */
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 430000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", false, 430000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
/* IVA OPP5 - OPP-Nitro SpeedBin*/
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 500000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", false, 500000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
/* SGX OPP1 - OPP50 */
OPP_INITIALIZER("gpu", "dpll_per_m7x2_ck", "core", true, 153600000, OMAP4460_VDD_CORE_OPP50_UV),
@@ -279,11 +279,11 @@ static struct omap_opp_def __initdata omap446x_opp_def_list[] = {
/* FDIF OPP3 - OPP100 */
OPP_INITIALIZER("fdif", "fdif_fck", "core", true, 128000000, OMAP4460_VDD_CORE_OPP100_UV),
/* DSP OPP1 - OPP50 */
- OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", true, 232750000, OMAP4460_VDD_IVA_OPP50_UV),
+ OPP_INITIALIZER("dsp_c0", "virt_dsp_ck", "iva", true, 232750000, OMAP4460_VDD_IVA_OPP50_UV),
/* DSP OPP2 - OPP100 */
- OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", true, 465500000, OMAP4460_VDD_IVA_OPP100_UV),
+ OPP_INITIALIZER("dsp_c0", "virt_dsp_ck", "iva", true, 465500000, OMAP4460_VDD_IVA_OPP100_UV),
/* DSP OPP3 - OPPTB */
- OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", false, 496000000, OMAP4460_VDD_IVA_OPPTURBO_UV),
+ OPP_INITIALIZER("dsp_c0", "virt_dsp_ck", "iva", false, 496000000, OMAP4460_VDD_IVA_OPPTURBO_UV),
/* HSI OPP1 - OPP50 */
OPP_INITIALIZER("hsi", "hsi_fck", "core", true, 96000000, OMAP4460_VDD_CORE_OPP50_UV),
/* HSI OPP2 - OPP100 */
@@ -391,20 +391,20 @@ static struct omap_opp_def __initdata omap447x_opp_low_def_list[] = {
OPP_INITIALIZER("l3_main_1", "virt_l3_ck", "core", true, 200000000, OMAP4470_VDD_CORE_OPP100_UV),
OPP_INITIALIZER("l3_main_1", "virt_l3_ck", "core", true, 200000000, OMAP4470_VDD_CORE_OPP100_OV_UV),
/* IVA OPP1 - OPP50 */
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 133000000, OMAP4470_VDD_IVA_OPP50_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", true, 133000000, OMAP4470_VDD_IVA_OPP50_UV),
/* IVA OPP2 - OPP100 */
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 266100000, OMAP4470_VDD_IVA_OPP100_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", true, 266100000, OMAP4470_VDD_IVA_OPP100_UV),
/*
* IVA OPP3 - OPP-Turbo + Disabled as the reference schematics
* recommends Phoenix VCORE2 which can supply only 600mA - so the ones
* above this OPP frequency, even though OMAP is capable, should be
* enabled by board file which is sure of the chip power capability
*/
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 332000000, OMAP4470_VDD_IVA_OPPTURBO_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", false, 332000000, OMAP4470_VDD_IVA_OPPTURBO_UV),
/* IVA OPP4 - OPP-Nitro */
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 430000000, OMAP4470_VDD_IVA_OPPNITRO_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", false, 430000000, OMAP4470_VDD_IVA_OPPNITRO_UV),
/* IVA OPP5 - OPP-Nitro SpeedBin*/
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 500000000, OMAP4470_VDD_IVA_OPPNITRO_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", false, 500000000, OMAP4470_VDD_IVA_OPPNITRO_UV),
/* SGX OPP1 - OPP50 */
OPP_INITIALIZER("gpu", "dpll_per_m7x2_ck", "core", true, 153600000, OMAP4470_VDD_CORE_OPP50_UV),
@@ -419,11 +419,11 @@ static struct omap_opp_def __initdata omap447x_opp_low_def_list[] = {
/* FDIF OPP3 - OPP100 */
OPP_INITIALIZER("fdif", "fdif_fck", "core", true, 128000000, OMAP4470_VDD_CORE_OPP100_UV),
/* DSP OPP1 - OPP50 */
- OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", true, 232750000, OMAP4470_VDD_IVA_OPP50_UV),
+ OPP_INITIALIZER("dsp_c0", "virt_dsp_ck", "iva", true, 232750000, OMAP4470_VDD_IVA_OPP50_UV),
/* DSP OPP2 - OPP100 */
- OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", true, 465500000, OMAP4470_VDD_IVA_OPP100_UV),
+ OPP_INITIALIZER("dsp_c0", "virt_dsp_ck", "iva", true, 465500000, OMAP4470_VDD_IVA_OPP100_UV),
/* DSP OPP3 - OPPTB */
- OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", false, 496000000, OMAP4470_VDD_IVA_OPPTURBO_UV),
+ OPP_INITIALIZER("dsp_c0", "virt_dsp_ck", "iva", false, 496000000, OMAP4470_VDD_IVA_OPPTURBO_UV),
/* HSI OPP1 - OPP50 */
OPP_INITIALIZER("hsi", "hsi_fck", "core", true, 96000000, OMAP4470_VDD_CORE_OPP50_UV),
/* HSI OPP2 - OPP100 */
@@ -451,20 +451,20 @@ static struct omap_opp_def __initdata omap447x_opp_high_def_list[] = {
/* L3 OPP3 - OPP-OV */
OPP_INITIALIZER("l3_main_1", "virt_l3_ck", "core", true, 233000000, OMAP4470_VDD_CORE_OPP100_OV_UV),
/* IVA OPP1 - OPP50 */
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 133000000, OMAP4470_VDD_IVA_OPP50_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", true, 133000000, OMAP4470_VDD_IVA_OPP50_UV),
/* IVA OPP2 - OPP100 */
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", true, 266100000, OMAP4470_VDD_IVA_OPP100_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", true, 266100000, OMAP4470_VDD_IVA_OPP100_UV),
/*
* IVA OPP3 - OPP-Turbo + Disabled as the reference schematics
* recommends Phoenix VCORE2 which can supply only 600mA - so the ones
* above this OPP frequency, even though OMAP is capable, should be
* enabled by board file which is sure of the chip power capability
*/
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 332000000, OMAP4470_VDD_IVA_OPPTURBO_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", false, 332000000, OMAP4470_VDD_IVA_OPPTURBO_UV),
/* IVA OPP4 - OPP-Nitro */
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 430000000, OMAP4470_VDD_IVA_OPPNITRO_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", false, 430000000, OMAP4470_VDD_IVA_OPPNITRO_UV),
/* IVA OPP5 - OPP-Nitro SpeedBin*/
- OPP_INITIALIZER("iva", "dpll_iva_m5x2_ck", "iva", false, 500000000, OMAP4470_VDD_IVA_OPPNITRO_UV),
+ OPP_INITIALIZER("iva", "virt_iva_ck", "iva", false, 500000000, OMAP4470_VDD_IVA_OPPNITRO_UV),
/* SGX OPP1 - OPP50 */
OPP_INITIALIZER("gpu", "dpll_per_m7x2_ck", "core", true, 192000000, OMAP4470_VDD_CORE_OPP50_UV),
@@ -478,11 +478,11 @@ static struct omap_opp_def __initdata omap447x_opp_high_def_list[] = {
/* FDIF OPP3 - OPP100 */
OPP_INITIALIZER("fdif", "fdif_fck", "core", true, 128000000, OMAP4470_VDD_CORE_OPP100_UV),
/* DSP OPP1 - OPP50 */
- OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", true, 232750000, OMAP4470_VDD_IVA_OPP50_UV),
+ OPP_INITIALIZER("dsp_c0", "virt_dsp_ck", "iva", true, 232750000, OMAP4470_VDD_IVA_OPP50_UV),
/* DSP OPP2 - OPP100 */
- OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", true, 465500000, OMAP4470_VDD_IVA_OPP100_UV),
+ OPP_INITIALIZER("dsp_c0", "virt_dsp_ck", "iva", true, 465500000, OMAP4470_VDD_IVA_OPP100_UV),
/* DSP OPP3 - OPPTB */
- OPP_INITIALIZER("dsp_c0", "dpll_iva_m4x2_ck", "iva", false, 496000000, OMAP4470_VDD_IVA_OPPTURBO_UV),
+ OPP_INITIALIZER("dsp_c0", "virt_dsp_ck", "iva", false, 496000000, OMAP4470_VDD_IVA_OPPTURBO_UV),
/* HSI OPP1 - OPP50 */
OPP_INITIALIZER("hsi", "hsi_fck", "core", true, 96000000, OMAP4470_VDD_CORE_OPP50_UV),
/* HSI OPP2 - OPP100 */
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9eb077d..a8eb978 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -472,7 +472,7 @@ static void __init omap4_init_voltages(void)
omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev);
}
omap2_set_init_voltage("core", "virt_l3_ck", l3_dev);
- omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev);
+ omap2_set_init_voltage("iva", "virt_iva_ck", iva_dev);
}
static int __init omap2_common_pm_init(void)
generated by cgit v1.1 at 2025-02-09 14:02:52 +0000