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-rw-r--r--drivers/gpu/pvr/bridged_pvr_bridge.c184
-rw-r--r--drivers/gpu/pvr/device.h11
-rw-r--r--drivers/gpu/pvr/mnemedefs.h94
-rw-r--r--drivers/gpu/pvr/mutils.h2
-rw-r--r--drivers/gpu/pvr/osfunc.c84
-rw-r--r--drivers/gpu/pvr/osfunc.h10
-rw-r--r--drivers/gpu/pvr/pvrsrv.c38
-rw-r--r--drivers/gpu/pvr/pvrversion.h4
-rw-r--r--drivers/gpu/pvr/queue.c34
-rw-r--r--drivers/gpu/pvr/servicesext.h220
-rw-r--r--drivers/gpu/pvr/sgx/sgxconfig.h19
-rw-r--r--drivers/gpu/pvr/sgx/sgxinit.c145
-rw-r--r--drivers/gpu/pvr/sgx/sgxkick.c2
-rw-r--r--drivers/gpu/pvr/sgx/sgxpower.c10
-rw-r--r--drivers/gpu/pvr/sgx/sgxreset.c10
-rw-r--r--drivers/gpu/pvr/sgx/sgxtransfer.c58
-rw-r--r--drivers/gpu/pvr/sgx/sgxutils.c92
-rw-r--r--drivers/gpu/pvr/sgx/sgxutils.h8
-rw-r--r--drivers/gpu/pvr/sgx543defs.h1256
-rw-r--r--drivers/gpu/pvr/sgxinfo.h1
-rw-r--r--drivers/gpu/pvr/sgxmpdefs.h306
21 files changed, 2160 insertions, 428 deletions
diff --git a/drivers/gpu/pvr/bridged_pvr_bridge.c b/drivers/gpu/pvr/bridged_pvr_bridge.c
index 7677329..f0dde10 100644
--- a/drivers/gpu/pvr/bridged_pvr_bridge.c
+++ b/drivers/gpu/pvr/bridged_pvr_bridge.c
@@ -147,7 +147,6 @@ PVRSRVAcquireDeviceDataBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-
psAcquireDevInfoOUT->eError =
PVRSRVAllocHandle(psPerProc->psHandleBase,
&psAcquireDevInfoOUT->hDevCookie,
@@ -172,7 +171,6 @@ PVRSRVCreateDeviceMemContextBW(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CREATE_DEVMEMCONTEXT);
-
NEW_HANDLE_BATCH_OR_ERROR(psCreateDevMemContextOUT->eError, psPerProc, PVRSRV_MAX_CLIENT_HEAPS + 1)
psCreateDevMemContextOUT->eError =
@@ -199,7 +197,7 @@ PVRSRVCreateDeviceMemContextBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-
+
if(bCreated)
{
PVRSRVAllocHandleNR(psPerProc->psHandleBase,
@@ -229,7 +227,7 @@ PVRSRVCreateDeviceMemContextBW(IMG_UINT32 ui32BridgeID,
if(abSharedDeviceMemHeap[i])
#endif
{
-
+
PVRSRVAllocHandleNR(psPerProc->psHandleBase, &hDevMemHeapExt,
psCreateDevMemContextOUT->sHeapInfo[i].hDevMemHeap,
PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP,
@@ -238,7 +236,7 @@ PVRSRVCreateDeviceMemContextBW(IMG_UINT32 ui32BridgeID,
#if defined(PVR_SECURE_HANDLES)
else
{
-
+
if(bCreated)
{
PVRSRVAllocSubHandleNR(psPerProc->psHandleBase, &hDevMemHeapExt,
@@ -374,7 +372,7 @@ PVRSRVGetDeviceMemHeapInfoBW(IMG_UINT32 ui32BridgeID,
if(abSharedDeviceMemHeap[i])
#endif
{
-
+
PVRSRVAllocHandleNR(psPerProc->psHandleBase, &hDevMemHeapExt,
psGetDevMemHeapInfoOUT->sHeapInfo[i].hDevMemHeap,
PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP,
@@ -383,7 +381,7 @@ PVRSRVGetDeviceMemHeapInfoBW(IMG_UINT32 ui32BridgeID,
#if defined(PVR_SECURE_HANDLES)
else
{
-
+
psGetDevMemHeapInfoOUT->eError =
PVRSRVFindHandle(psPerProc->psHandleBase, &hDevMemHeapExt,
psGetDevMemHeapInfoOUT->sHeapInfo[i].hDevMemHeap,
@@ -484,7 +482,7 @@ PVRSRVAllocDeviceMemBW(IMG_UINT32 ui32BridgeID,
if(psAllocDeviceMemIN->ui32Attribs & PVRSRV_MEM_NO_SYNCOBJ)
{
-
+
OSMemSet(&psAllocDeviceMemOUT->sClientSyncInfo,
0,
sizeof (PVRSRV_CLIENT_SYNC_INFO));
@@ -492,7 +490,7 @@ PVRSRVAllocDeviceMemBW(IMG_UINT32 ui32BridgeID,
}
else
{
-
+
psAllocDeviceMemOUT->sClientSyncInfo.psSyncData =
psMemInfo->psKernelSyncInfo->psSyncData;
@@ -521,7 +519,7 @@ PVRSRVAllocDeviceMemBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-#endif
+#endif
static IMG_INT
PVRSRVFreeDeviceMemBW(IMG_UINT32 ui32BridgeID,
@@ -582,7 +580,7 @@ PVRSRVExportDeviceMemBW(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_EXPORT_DEVICEMEM);
-
+
psExportDeviceMemOUT->eError =
PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt,
psExportDeviceMemIN->hDevCookie,
@@ -594,7 +592,7 @@ PVRSRVExportDeviceMemBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-
+
psExportDeviceMemOUT->eError =
PVRSRVLookupHandle(psPerProc->psHandleBase, (IMG_PVOID *)&psKernelMemInfo,
psExportDeviceMemIN->psKernelMemInfo,
@@ -606,7 +604,7 @@ PVRSRVExportDeviceMemBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-
+
psExportDeviceMemOUT->eError =
PVRSRVFindHandle(KERNEL_HANDLE_BASE,
&psExportDeviceMemOUT->hMemInfo,
@@ -614,12 +612,12 @@ PVRSRVExportDeviceMemBW(IMG_UINT32 ui32BridgeID,
PVRSRV_HANDLE_TYPE_MEM_INFO);
if(psExportDeviceMemOUT->eError == PVRSRV_OK)
{
-
+
PVR_DPF((PVR_DBG_MESSAGE, "PVRSRVExportDeviceMemBW: allocation is already exported"));
return 0;
}
-
+
psExportDeviceMemOUT->eError = PVRSRVAllocHandle(KERNEL_HANDLE_BASE,
&psExportDeviceMemOUT->hMemInfo,
psKernelMemInfo,
@@ -631,7 +629,7 @@ PVRSRVExportDeviceMemBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-
+
psKernelMemInfo->ui32Flags |= PVRSRV_MEM_EXPORTED;
return 0;
@@ -652,7 +650,7 @@ PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
NEW_HANDLE_BATCH_OR_ERROR(psMapDevMemOUT->eError, psPerProc, 2)
-
+
psMapDevMemOUT->eError = PVRSRVLookupHandle(KERNEL_HANDLE_BASE,
(IMG_VOID**)&psSrcKernelMemInfo,
psMapDevMemIN->hKernelMemInfo,
@@ -662,7 +660,7 @@ PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-
+
psMapDevMemOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
&hDstDevMemHeap,
psMapDevMemIN->hDstDevMemHeap,
@@ -672,7 +670,7 @@ PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-
+
psMapDevMemOUT->eError = PVRSRVMapDeviceMemoryKM(psPerProc,
psSrcKernelMemInfo,
hDstDevMemHeap,
@@ -698,7 +696,7 @@ PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
psMapDevMemOUT->sDstClientMemInfo.ui32AllocSize = psDstKernelMemInfo->ui32AllocSize;
psMapDevMemOUT->sDstClientMemInfo.hMappingInfo = psDstKernelMemInfo->sMemBlk.hOSMemHandle;
-
+
PVRSRVAllocHandleNR(psPerProc->psHandleBase,
&psMapDevMemOUT->sDstClientMemInfo.hKernelMemInfo,
psDstKernelMemInfo,
@@ -706,7 +704,7 @@ PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
PVRSRV_HANDLE_ALLOC_FLAG_NONE);
psMapDevMemOUT->sDstClientSyncInfo.hKernelSyncInfo = IMG_NULL;
-
+
if(psDstKernelMemInfo->psKernelSyncInfo)
{
psMapDevMemOUT->sDstClientSyncInfo.psSyncData =
@@ -720,7 +718,7 @@ PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
psDstKernelMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle;
psMapDevMemOUT->sDstClientMemInfo.psClientSyncInfo = &psMapDevMemOUT->sDstClientSyncInfo;
-
+
PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
&psMapDevMemOUT->sDstClientSyncInfo.hKernelSyncInfo,
psDstKernelMemInfo->psKernelSyncInfo,
@@ -785,7 +783,7 @@ PVRSRVMapDeviceClassMemoryBW(IMG_UINT32 ui32BridgeID,
NEW_HANDLE_BATCH_OR_ERROR(psMapDevClassMemOUT->eError, psPerProc, 2)
-
+
psMapDevClassMemOUT->eError =
PVRSRVLookupHandleAnyType(psPerProc->psHandleBase, &hDeviceClassBufferInt,
&eHandleType,
@@ -1699,7 +1697,7 @@ PVRSRVConnectBW(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CONNECT_SERVICES);
#if defined(PDUMP)
-
+
psPerProc->bPDumpPersistent |= ( (psConnectServicesIN->ui32Flags & SRV_FLAGS_PERSIST) != 0) ? IMG_TRUE : IMG_FALSE;
#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
@@ -1726,7 +1724,7 @@ PVRSRVDisconnectBW(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_DISCONNECT_SERVICES);
-
+
psRetOUT->eError = PVRSRV_OK;
return 0;
@@ -1888,7 +1886,7 @@ PVRSRVEnumDCDimsBW(IMG_UINT32 ui32BridgeID,
static IMG_INT
PVRSRVGetDCSystemBufferBW(IMG_UINT32 ui32BridgeID,
- PVRSRV_BRIDGE_IN_GET_DISPCLASS_SYSBUFFER *psGetDispClassSysBufferIN,
+ PVRSRV_BRIDGE_IN_GET_DISPCLASS_SYSBUFFER *psGetDispClassSysBufferIN,
PVRSRV_BRIDGE_OUT_GET_DISPCLASS_SYSBUFFER *psGetDispClassSysBufferOUT,
PVRSRV_PER_PROCESS_DATA *psPerProc)
{
@@ -1918,7 +1916,7 @@ PVRSRVGetDCSystemBufferBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-
+
PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
&psGetDispClassSysBufferOUT->hBuffer,
hBufferInt,
@@ -1983,7 +1981,7 @@ PVRSRVCreateDCSwapChainBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-
+
ui32SwapChainID = psCreateDispClassSwapChainIN->ui32SwapChainID;
psCreateDispClassSwapChainOUT->eError =
@@ -2001,7 +1999,7 @@ PVRSRVCreateDCSwapChainBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-
+
psCreateDispClassSwapChainOUT->ui32SwapChainID = ui32SwapChainID;
PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
@@ -2258,7 +2256,7 @@ PVRSRVGetDCBuffersBW(IMG_UINT32 ui32BridgeID,
{
IMG_HANDLE hBufferExt;
-
+
PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
&hBufferExt,
psGetDispClassBuffersOUT->ahBuffer[i],
@@ -2493,7 +2491,7 @@ PVRSRVGetBCBufferBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-
+
PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
&psGetBufferClassBufferOUT->hBuffer,
hBufferInt,
@@ -2623,7 +2621,7 @@ PVRSRVMapMemInfoMemBW(IMG_UINT32 ui32BridgeID,
return 0;
}
-
+
psMapMemInfoMemOUT->eError =
PVRSRVGetParentHandle(psPerProc->psHandleBase,
&hParent,
@@ -2663,14 +2661,14 @@ PVRSRVMapMemInfoMemBW(IMG_UINT32 ui32BridgeID,
if(psKernelMemInfo->ui32Flags & PVRSRV_MEM_NO_SYNCOBJ)
{
-
+
OSMemSet(&psMapMemInfoMemOUT->sClientSyncInfo,
0,
sizeof (PVRSRV_CLIENT_SYNC_INFO));
}
else
{
-
+
psMapMemInfoMemOUT->sClientSyncInfo.psSyncData =
psKernelMemInfo->psKernelSyncInfo->psSyncData;
psMapMemInfoMemOUT->sClientSyncInfo.sWriteOpsCompleteDevVAddr =
@@ -2764,7 +2762,7 @@ _SetDispatchTableEntry(IMG_UINT32 ui32Index,
BridgeWrapperFunction pfFunction,
const IMG_CHAR *pszFunctionName)
{
- static IMG_UINT32 ui32PrevIndex = ~0UL;
+ static IMG_UINT32 ui32PrevIndex = ~0UL;
#if !defined(DEBUG)
PVR_UNREFERENCED_PARAMETER(pszIOCName);
#endif
@@ -2773,11 +2771,11 @@ _SetDispatchTableEntry(IMG_UINT32 ui32Index,
#endif
#if defined(DEBUG_BRIDGE_KM_DISPATCH_TABLE)
-
+
PVR_DPF((PVR_DBG_WARNING, "%s: %d %s %s", __FUNCTION__, ui32Index, pszIOCName, pszFunctionName));
#endif
-
+
if(g_BridgeDispatchTable[ui32Index].pfFunction)
{
#if defined(DEBUG_BRIDGE_KM)
@@ -2792,7 +2790,7 @@ _SetDispatchTableEntry(IMG_UINT32 ui32Index,
PVR_DPF((PVR_DBG_ERROR, "NOTE: Enabling DEBUG_BRIDGE_KM_DISPATCH_TABLE may help debug this issue."));
}
-
+
if((ui32PrevIndex != ~0UL) &&
((ui32Index >= ui32PrevIndex + DISPATCH_TABLE_GAP_THRESHOLD) ||
(ui32Index <= ui32PrevIndex)))
@@ -2832,7 +2830,7 @@ PVRSRVInitSrvConnectBW(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_INITSRV_CONNECT);
PVR_UNREFERENCED_PARAMETER(psBridgeIn);
-
+
if((OSProcHasPrivSrvInit() == IMG_FALSE) || PVRSRVGetInitServerState(PVRSRV_INIT_SERVER_RUNNING) || PVRSRVGetInitServerState(PVRSRV_INIT_SERVER_RAN))
{
psRetOUT->eError = PVRSRV_ERROR_SRV_CONNECT_FAILED;
@@ -2986,7 +2984,7 @@ typedef struct _MODIFY_SYNC_OP_INFO
{
IMG_HANDLE hResItem;
PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
- IMG_UINT32 ui32ModifyFlags;
+ IMG_UINT32 ui32ModifyFlags;
IMG_UINT32 ui32ReadOpsPendingSnapShot;
IMG_UINT32 ui32WriteOpsPendingSnapShot;
} MODIFY_SYNC_OP_INFO;
@@ -3007,7 +3005,7 @@ static PVRSRV_ERROR DoQuerySyncOpsSatisfied(MODIFY_SYNC_OP_INFO *psModSyncOpInfo
&& (psModSyncOpInfo->ui32ReadOpsPendingSnapShot == psKernelSyncInfo->psSyncData->ui32ReadOpsComplete))
{
#if defined(PDUMP)
-
+
PDumpComment("Poll for read ops complete to reach value (%u)", psModSyncOpInfo->ui32ReadOpsPendingSnapShot);
@@ -3018,8 +3016,8 @@ static PVRSRV_ERROR DoQuerySyncOpsSatisfied(MODIFY_SYNC_OP_INFO *psModSyncOpInfo
PDUMP_POLL_OPERATOR_EQUAL,
0,
MAKEUNIQUETAG(psKernelSyncInfo->psSyncDataMemInfoKM));
-
-
+
+
PDumpComment("Poll for write ops complete to reach value (%u)", psModSyncOpInfo->ui32WriteOpsPendingSnapShot);
PDumpMemPolKM(psKernelSyncInfo->psSyncDataMemInfoKM,
offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete),
@@ -3048,20 +3046,20 @@ static PVRSRV_ERROR DoModifyCompleteSyncOps(MODIFY_SYNC_OP_INFO *psModSyncOpInfo
return PVRSRV_ERROR_INVALID_PARAMS;
}
-
+
if((psModSyncOpInfo->ui32WriteOpsPendingSnapShot != psKernelSyncInfo->psSyncData->ui32WriteOpsComplete)
|| (psModSyncOpInfo->ui32ReadOpsPendingSnapShot != psKernelSyncInfo->psSyncData->ui32ReadOpsComplete))
{
return PVRSRV_ERROR_BAD_SYNC_STATE;
}
-
-
+
+
if(psModSyncOpInfo->ui32ModifyFlags & PVRSRV_MODIFYSYNCOPS_FLAGS_WO_INC)
{
psKernelSyncInfo->psSyncData->ui32WriteOpsComplete++;
}
-
-
+
+
if(psModSyncOpInfo->ui32ModifyFlags & PVRSRV_MODIFYSYNCOPS_FLAGS_RO_INC)
{
psKernelSyncInfo->psSyncData->ui32ReadOpsComplete++;
@@ -3088,7 +3086,7 @@ static PVRSRV_ERROR ModifyCompleteSyncOpsCallBack(IMG_PVOID pvParam,
if (psModSyncOpInfo->psKernelSyncInfo)
{
-
+
LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US)
{
if (DoQuerySyncOpsSatisfied(psModSyncOpInfo) == PVRSRV_OK)
@@ -3096,9 +3094,9 @@ static PVRSRV_ERROR ModifyCompleteSyncOpsCallBack(IMG_PVOID pvParam,
goto OpFlushedComplete;
}
PVR_DPF((PVR_DBG_WARNING, "ModifyCompleteSyncOpsCallBack: waiting for current Ops to flush"));
- OSWaitus(MAX_HW_TIME_US/WAIT_TRY_COUNT);
+ OSSleepms(1);
} END_LOOP_UNTIL_TIMEOUT();
-
+
PVR_DPF((PVR_DBG_ERROR, "ModifyCompleteSyncOpsCallBack: timeout whilst waiting for current Ops to flush."));
PVR_DPF((PVR_DBG_ERROR, " Write ops pending snapshot = %d, write ops complete = %d",
psModSyncOpInfo->ui32WriteOpsPendingSnapShot,
@@ -3106,18 +3104,18 @@ static PVRSRV_ERROR ModifyCompleteSyncOpsCallBack(IMG_PVOID pvParam,
PVR_DPF((PVR_DBG_ERROR, " Read ops pending snapshot = %d, write ops complete = %d",
psModSyncOpInfo->ui32ReadOpsPendingSnapShot,
psModSyncOpInfo->psKernelSyncInfo->psSyncData->ui32ReadOpsComplete));
-
+
return PVRSRV_ERROR_TIMEOUT;
-
+
OpFlushedComplete:
-
+
DoModifyCompleteSyncOps(psModSyncOpInfo);
}
- OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(MODIFY_SYNC_OP_INFO), (IMG_VOID *)psModSyncOpInfo, 0);
-
+ OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(MODIFY_SYNC_OP_INFO), (IMG_VOID *)psModSyncOpInfo, 0);
+
+
-
PVRSRVScheduleDeviceCallbacks();
return PVRSRV_OK;
@@ -3128,7 +3126,7 @@ static IMG_INT
PVRSRVCreateSyncInfoModObjBW(IMG_UINT32 ui32BridgeID,
IMG_VOID *psBridgeIn,
PVRSRV_BRIDGE_OUT_CREATE_SYNC_INFO_MOD_OBJ *psCreateSyncInfoModObjOUT,
- PVRSRV_PER_PROCESS_DATA *psPerProc)
+ PVRSRV_PER_PROCESS_DATA *psPerProc)
{
MODIFY_SYNC_OP_INFO *psModSyncOpInfo;
@@ -3144,7 +3142,7 @@ PVRSRVCreateSyncInfoModObjBW(IMG_UINT32
(IMG_VOID **)&psModSyncOpInfo, 0,
"ModSyncOpInfo (MODIFY_SYNC_OP_INFO)"));
- psModSyncOpInfo->psKernelSyncInfo = IMG_NULL;
+ psModSyncOpInfo->psKernelSyncInfo = IMG_NULL;
psCreateSyncInfoModObjOUT->eError = PVRSRVAllocHandle(psPerProc->psHandleBase,
&psCreateSyncInfoModObjOUT->hKernelSyncInfoModObj,
@@ -3173,7 +3171,7 @@ static IMG_INT
PVRSRVDestroySyncInfoModObjBW(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_DESTROY_SYNC_INFO_MOD_OBJ *psDestroySyncInfoModObjIN,
PVRSRV_BRIDGE_RETURN *psDestroySyncInfoModObjOUT,
- PVRSRV_PER_PROCESS_DATA *psPerProc)
+ PVRSRV_PER_PROCESS_DATA *psPerProc)
{
MODIFY_SYNC_OP_INFO *psModSyncOpInfo;
@@ -3191,7 +3189,7 @@ PVRSRVDestroySyncInfoModObjBW(IMG_UINT32
if(psModSyncOpInfo->psKernelSyncInfo != IMG_NULL)
{
-
+
psDestroySyncInfoModObjOUT->eError = PVRSRV_ERROR_INVALID_PARAMS;
return 0;
}
@@ -3215,7 +3213,7 @@ PVRSRVDestroySyncInfoModObjBW(IMG_UINT32
return 0;
}
-
+
static IMG_INT
PVRSRVModifyPendingSyncOpsBW(IMG_UINT32 ui32BridgeID,
@@ -3250,19 +3248,19 @@ PVRSRVModifyPendingSyncOpsBW(IMG_UINT32 ui32BridgeID,
if(psModSyncOpInfo->psKernelSyncInfo)
{
-
+
psModifySyncOpsOUT->eError = PVRSRV_ERROR_RETRY;
PVR_DPF((PVR_DBG_VERBOSE, "PVRSRVModifyPendingSyncOpsBW: SyncInfo Modification object is not empty"));
return 0;
}
-
+
psModSyncOpInfo->psKernelSyncInfo = psKernelSyncInfo;
psModSyncOpInfo->ui32ModifyFlags = psModifySyncOpsIN->ui32ModifyFlags;
psModSyncOpInfo->ui32ReadOpsPendingSnapShot = psKernelSyncInfo->psSyncData->ui32ReadOpsPending;
psModSyncOpInfo->ui32WriteOpsPendingSnapShot = psKernelSyncInfo->psSyncData->ui32WriteOpsPending;
-
+
psModifySyncOpsOUT->ui32ReadOpsPending = psKernelSyncInfo->psSyncData->ui32ReadOpsPending;
psModifySyncOpsOUT->ui32WriteOpsPending = psKernelSyncInfo->psSyncData->ui32WriteOpsPending;
@@ -3277,7 +3275,7 @@ PVRSRVModifyPendingSyncOpsBW(IMG_UINT32 ui32BridgeID,
psKernelSyncInfo->psSyncData->ui32ReadOpsPending++;
}
-
+
psModifySyncOpsOUT->eError = ResManDissociateRes(psModSyncOpInfo->hResItem,
psPerProc->hResManContext);
@@ -3313,7 +3311,7 @@ PVRSRVModifyCompleteSyncOpsBW(IMG_UINT32 ui32BridgeID,
if(psModSyncOpInfo->psKernelSyncInfo == IMG_NULL)
{
-
+
psModifySyncOpsOUT->eError = PVRSRV_ERROR_INVALID_PARAMS;
return 0;
}
@@ -3328,7 +3326,7 @@ PVRSRVModifyCompleteSyncOpsBW(IMG_UINT32 ui32BridgeID,
psModSyncOpInfo->psKernelSyncInfo = IMG_NULL;
-
+
PVRSRVScheduleDeviceCallbacks();
return 0;
@@ -3339,7 +3337,7 @@ static IMG_INT
PVRSRVSyncOpsFlushToModObjBW(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_MOD_OBJ *psSyncOpsFlushToModObjIN,
PVRSRV_BRIDGE_RETURN *psSyncOpsFlushToModObjOUT,
- PVRSRV_PER_PROCESS_DATA *psPerProc)
+ PVRSRV_PER_PROCESS_DATA *psPerProc)
{
MODIFY_SYNC_OP_INFO *psModSyncOpInfo;
@@ -3357,7 +3355,7 @@ PVRSRVSyncOpsFlushToModObjBW(IMG_UINT32
if(psModSyncOpInfo->psKernelSyncInfo == IMG_NULL)
{
-
+
psSyncOpsFlushToModObjOUT->eError = PVRSRV_ERROR_INVALID_PARAMS;
return 0;
}
@@ -3378,7 +3376,7 @@ static IMG_INT
PVRSRVSyncOpsFlushToDeltaBW(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_DELTA *psSyncOpsFlushToDeltaIN,
PVRSRV_BRIDGE_RETURN *psSyncOpsFlushToDeltaOUT,
- PVRSRV_PER_PROCESS_DATA *psPerProc)
+ PVRSRV_PER_PROCESS_DATA *psPerProc)
{
PVRSRV_KERNEL_SYNC_INFO *psSyncInfo;
IMG_UINT32 ui32DeltaRead;
@@ -3414,7 +3412,7 @@ PVRSRVSyncOpsFlushToDeltaBW(IMG_UINT32 u
ui32MinimumReadOpsComplete = ui32MinimumReadOpsComplete - psSyncOpsFlushToDeltaIN->ui32Delta;
}
-
+
PDumpComment("Poll for read ops complete to delta (%u)",
psSyncOpsFlushToDeltaIN->ui32Delta);
psSyncOpsFlushToDeltaOUT->eError =
@@ -3426,7 +3424,7 @@ PVRSRVSyncOpsFlushToDeltaBW(IMG_UINT32 u
0,
MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM));
-
+
PDumpComment("Poll for write ops complete to delta (%u)",
psSyncOpsFlushToDeltaIN->ui32Delta);
psSyncOpsFlushToDeltaOUT->eError =
@@ -3466,7 +3464,7 @@ FreeSyncInfoCallback(IMG_PVOID pvParam,
{
return eError;
}
-
+
return PVRSRV_OK;
}
@@ -3475,13 +3473,13 @@ static IMG_INT
PVRSRVAllocSyncInfoBW(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_ALLOC_SYNC_INFO *psAllocSyncInfoIN,
PVRSRV_BRIDGE_OUT_ALLOC_SYNC_INFO *psAllocSyncInfoOUT,
- PVRSRV_PER_PROCESS_DATA *psPerProc)
+ PVRSRV_PER_PROCESS_DATA *psPerProc)
{
PVRSRV_KERNEL_SYNC_INFO *psSyncInfo;
PVRSRV_ERROR eError;
PVRSRV_DEVICE_NODE *psDeviceNode;
IMG_HANDLE hDevMemContext;
-
+
PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ALLOC_SYNC_INFO);
NEW_HANDLE_BATCH_OR_ERROR(psAllocSyncInfoOUT->eError, psPerProc, 1)
@@ -3496,11 +3494,11 @@ PVRSRVAllocSyncInfoBW(IMG_UINT32 ui32Bri
}
hDevMemContext = psDeviceNode->sDevMemoryInfo.pBMKernelContext;
-
+
eError = PVRSRVAllocSyncInfoKM(psDeviceNode,
hDevMemContext,
&psSyncInfo);
-
+
if (eError != PVRSRV_OK)
{
goto allocsyncinfo_errorexit;
@@ -3523,20 +3521,20 @@ PVRSRVAllocSyncInfoBW(IMG_UINT32 ui32Bri
0,
FreeSyncInfoCallback);
-
+
goto allocsyncinfo_commit;
-
-
+
+
allocsyncinfo_errorexit_freesyncinfo:
PVRSRVFreeSyncInfoKM(psSyncInfo);
allocsyncinfo_errorexit:
-
+
allocsyncinfo_commit:
psAllocSyncInfoOUT->eError = eError;
COMMIT_HANDLE_BATCH_OR_ERROR(eError, psPerProc);
-
+
return 0;
}
@@ -3545,7 +3543,7 @@ static IMG_INT
PVRSRVFreeSyncInfoBW(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_FREE_SYNC_INFO *psFreeSyncInfoIN,
PVRSRV_BRIDGE_RETURN *psFreeSyncInfoOUT,
- PVRSRV_PER_PROCESS_DATA *psPerProc)
+ PVRSRV_PER_PROCESS_DATA *psPerProc)
{
PVRSRV_KERNEL_SYNC_INFO *psSyncInfo;
PVRSRV_ERROR eError;
@@ -3620,30 +3618,30 @@ CommonBridgeInit(IMG_VOID)
SetDispatchTableEntry(PVRSRV_BRIDGE_EXPORT_DEVICEMEM, PVRSRVExportDeviceMemBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_RELEASE_MMAP_DATA, PVRMMapReleaseMMapDataBW);
-
+
SetDispatchTableEntry(PVRSRV_BRIDGE_PROCESS_SIMISR_EVENT, DummyBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_REGISTER_SIM_PROCESS, DummyBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_UNREGISTER_SIM_PROCESS, DummyBW);
-
+
SetDispatchTableEntry(PVRSRV_BRIDGE_MAPPHYSTOUSERSPACE, DummyBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_UNMAPPHYSTOUSERSPACE, DummyBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_GETPHYSTOUSERSPACEMAP, DummyBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_GET_FB_STATS, DummyBW);
-
+
SetDispatchTableEntry(PVRSRV_BRIDGE_GET_MISC_INFO, PVRSRVGetMiscInfoBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_RELEASE_MISC_INFO, DummyBW);
-
+
#if defined (SUPPORT_OVERLAY_ROTATE_BLIT)
SetDispatchTableEntry(PVRSRV_BRIDGE_INIT_3D_OVL_BLT_RES, DummyBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_DEINIT_3D_OVL_BLT_RES, DummyBW);
#endif
-
+
#if defined(PDUMP)
SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_INIT, DummyBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_MEMPOL, PDumpMemPolBW);
@@ -3662,15 +3660,15 @@ CommonBridgeInit(IMG_VOID)
SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_CYCLE_COUNT_REG_READ, PDumpCycleCountRegReadBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_STARTINITPHASE, PDumpStartInitPhaseBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_STOPINITPHASE, PDumpStopInitPhaseBW);
-#endif
+#endif
+
-
SetDispatchTableEntry(PVRSRV_BRIDGE_GET_OEMJTABLE, DummyBW);
-
+
SetDispatchTableEntry(PVRSRV_BRIDGE_ENUM_CLASS, PVRSRVEnumerateDCBW);
-
+
SetDispatchTableEntry(PVRSRV_BRIDGE_OPEN_DISPCLASS_DEVICE, PVRSRVOpenDCDeviceBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_CLOSE_DISPCLASS_DEVICE, PVRSRVCloseDCDeviceBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_ENUM_DISPCLASS_FORMATS, PVRSRVEnumDCFormatsBW);
diff --git a/drivers/gpu/pvr/device.h b/drivers/gpu/pvr/device.h
index bed2351..f41bd9e 100644
--- a/drivers/gpu/pvr/device.h
+++ b/drivers/gpu/pvr/device.h
@@ -288,11 +288,12 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVDeinitialiseDevice(IMG_UINT32 ui32DevIndex);
#if !defined(USE_CODE)
-IMG_IMPORT PVRSRV_ERROR IMG_CALLCONV PollForValueKM(volatile IMG_UINT32* pui32LinMemAddr,
- IMG_UINT32 ui32Value,
- IMG_UINT32 ui32Mask,
- IMG_UINT32 ui32Waitus,
- IMG_UINT32 ui32Tries);
+IMG_IMPORT PVRSRV_ERROR IMG_CALLCONV PollForValueKM(volatile IMG_UINT32* pui32LinMemAddr,
+ IMG_UINT32 ui32Value,
+ IMG_UINT32 ui32Mask,
+ IMG_UINT32 ui32Timeoutus,
+ IMG_UINT32 ui32PollPeriodus,
+ IMG_BOOL bAllowPreemption);
#endif
diff --git a/drivers/gpu/pvr/mnemedefs.h b/drivers/gpu/pvr/mnemedefs.h
new file mode 100644
index 0000000..1a88031
--- /dev/null
+++ b/drivers/gpu/pvr/mnemedefs.h
@@ -0,0 +1,94 @@
+/**********************************************************************
+ *
+ * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful but, except
+ * as otherwise stated in writing, without any warranty; without even the
+ * implied warranty of merchantability or fitness for a particular purpose.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ *
+ * Contact Information:
+ * Imagination Technologies Ltd. <gpl-support@imgtec.com>
+ * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
+ *
+ ******************************************************************************/
+
+#ifndef _MNEMEDEFS_KM_H_
+#define _MNEMEDEFS_KM_H_
+
+#define MNE_CR_CTRL 0x0D00
+#define MNE_CR_CTRL_BYP_CC_N_MASK 0x00010000U
+#define MNE_CR_CTRL_BYP_CC_N_SHIFT 16
+#define MNE_CR_CTRL_BYP_CC_N_SIGNED 0
+#define MNE_CR_CTRL_BYP_CC_MASK 0x00008000U
+#define MNE_CR_CTRL_BYP_CC_SHIFT 15
+#define MNE_CR_CTRL_BYP_CC_SIGNED 0
+#define MNE_CR_CTRL_USE_INVAL_REQ_MASK 0x00007800U
+#define MNE_CR_CTRL_USE_INVAL_REQ_SHIFT 11
+#define MNE_CR_CTRL_USE_INVAL_REQ_SIGNED 0
+#define MNE_CR_CTRL_BYPASS_ALL_MASK 0x00000400U
+#define MNE_CR_CTRL_BYPASS_ALL_SHIFT 10
+#define MNE_CR_CTRL_BYPASS_ALL_SIGNED 0
+#define MNE_CR_CTRL_BYPASS_MASK 0x000003E0U
+#define MNE_CR_CTRL_BYPASS_SHIFT 5
+#define MNE_CR_CTRL_BYPASS_SIGNED 0
+#define MNE_CR_CTRL_PAUSE_MASK 0x00000010U
+#define MNE_CR_CTRL_PAUSE_SHIFT 4
+#define MNE_CR_CTRL_PAUSE_SIGNED 0
+#define MNE_CR_USE_INVAL 0x0D04
+#define MNE_CR_USE_INVAL_ADDR_MASK 0xFFFFFFFFU
+#define MNE_CR_USE_INVAL_ADDR_SHIFT 0
+#define MNE_CR_USE_INVAL_ADDR_SIGNED 0
+#define MNE_CR_STAT 0x0D08
+#define MNE_CR_STAT_PAUSED_MASK 0x00000400U
+#define MNE_CR_STAT_PAUSED_SHIFT 10
+#define MNE_CR_STAT_PAUSED_SIGNED 0
+#define MNE_CR_STAT_READS_MASK 0x000003FFU
+#define MNE_CR_STAT_READS_SHIFT 0
+#define MNE_CR_STAT_READS_SIGNED 0
+#define MNE_CR_STAT_STATS 0x0D0C
+#define MNE_CR_STAT_STATS_RST_MASK 0x000FFFF0U
+#define MNE_CR_STAT_STATS_RST_SHIFT 4
+#define MNE_CR_STAT_STATS_RST_SIGNED 0
+#define MNE_CR_STAT_STATS_SEL_MASK 0x0000000FU
+#define MNE_CR_STAT_STATS_SEL_SHIFT 0
+#define MNE_CR_STAT_STATS_SEL_SIGNED 0
+#define MNE_CR_STAT_STATS_OUT 0x0D10
+#define MNE_CR_STAT_STATS_OUT_VALUE_MASK 0xFFFFFFFFU
+#define MNE_CR_STAT_STATS_OUT_VALUE_SHIFT 0
+#define MNE_CR_STAT_STATS_OUT_VALUE_SIGNED 0
+#define MNE_CR_EVENT_STATUS 0x0D14
+#define MNE_CR_EVENT_STATUS_INVAL_MASK 0x00000001U
+#define MNE_CR_EVENT_STATUS_INVAL_SHIFT 0
+#define MNE_CR_EVENT_STATUS_INVAL_SIGNED 0
+#define MNE_CR_EVENT_CLEAR 0x0D18
+#define MNE_CR_EVENT_CLEAR_INVAL_MASK 0x00000001U
+#define MNE_CR_EVENT_CLEAR_INVAL_SHIFT 0
+#define MNE_CR_EVENT_CLEAR_INVAL_SIGNED 0
+#define MNE_CR_CTRL_INVAL 0x0D20
+#define MNE_CR_CTRL_INVAL_PREQ_PDS_MASK 0x00000008U
+#define MNE_CR_CTRL_INVAL_PREQ_PDS_SHIFT 3
+#define MNE_CR_CTRL_INVAL_PREQ_PDS_SIGNED 0
+#define MNE_CR_CTRL_INVAL_PREQ_USEC_MASK 0x00000004U
+#define MNE_CR_CTRL_INVAL_PREQ_USEC_SHIFT 2
+#define MNE_CR_CTRL_INVAL_PREQ_USEC_SIGNED 0
+#define MNE_CR_CTRL_INVAL_PREQ_CACHE_MASK 0x00000002U
+#define MNE_CR_CTRL_INVAL_PREQ_CACHE_SHIFT 1
+#define MNE_CR_CTRL_INVAL_PREQ_CACHE_SIGNED 0
+#define MNE_CR_CTRL_INVAL_ALL_MASK 0x00000001U
+#define MNE_CR_CTRL_INVAL_ALL_SHIFT 0
+#define MNE_CR_CTRL_INVAL_ALL_SIGNED 0
+
+#endif
+
diff --git a/drivers/gpu/pvr/mutils.h b/drivers/gpu/pvr/mutils.h
index 943c2bd..c42eadc 100644
--- a/drivers/gpu/pvr/mutils.h
+++ b/drivers/gpu/pvr/mutils.h
@@ -46,7 +46,7 @@
#if defined(__arm__) || defined(__sh__)
#define PGPROT_WC(pv) pgprot_writecombine(pv)
#else
- #if defined(__i386__)
+ #if defined(__i386__) || defined(__mips__)
#define PGPROT_WC(pv) pgprot_noncached(pv)
#else
#define PGPROT_WC(pv) pgprot_noncached(pv)
diff --git a/drivers/gpu/pvr/osfunc.c b/drivers/gpu/pvr/osfunc.c
index 7a9c476..ba3bf01 100644
--- a/drivers/gpu/pvr/osfunc.c
+++ b/drivers/gpu/pvr/osfunc.c
@@ -125,20 +125,20 @@ PVRSRV_ERROR OSAllocMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOI
return PVRSRV_ERROR_OUT_OF_MEMORY;
}
-
+
*phBlockAlloc = HOST_ALLOC_MEM_USING_VMALLOC;
}
return PVRSRV_OK;
}
-
+
#if !defined(DEBUG_LINUX_MEMORY_ALLOCATIONS)
PVRSRV_ERROR OSFreeMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOID pvCpuVAddr, IMG_HANDLE hBlockAlloc)
#else
PVRSRV_ERROR OSFreeMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOID pvCpuVAddr, IMG_HANDLE hBlockAlloc, IMG_CHAR *pszFilename, IMG_UINT32 ui32Line)
#endif
-{
+{
PVR_UNREFERENCED_PARAMETER(ui32Flags);
PVR_UNREFERENCED_PARAMETER(ui32Size);
@@ -512,13 +512,18 @@ IMG_UINT32 OSClockus(IMG_VOID)
}
-
IMG_VOID OSWaitus(IMG_UINT32 ui32Timeus)
{
udelay(ui32Timeus);
}
+IMG_VOID OSSleepms(IMG_UINT32 ui32Timems)
+{
+ msleep(ui32Timems);
+}
+
+
IMG_UINT32 OSGetCurrentProcessIDKM(IMG_VOID)
{
if (in_interrupt())
@@ -2679,29 +2684,51 @@ IMG_BOOL CheckExecuteCacheOp(IMG_HANDLE hOSMemHandle,
psLinuxMemArea = psLinuxMemArea->uData.sSubAlloc.psParentLinuxMemArea;
}
-
+
PVR_ASSERT(psLinuxMemArea->eAreaType != LINUX_MEM_AREA_SUB_ALLOC);
switch(psLinuxMemArea->eAreaType)
{
case LINUX_MEM_AREA_VMALLOC:
{
- pvMinVAddr = psLinuxMemArea->uData.sVmalloc.pvVmallocAddress + ui32AreaOffset;
+ if(is_vmalloc_addr(pvRangeAddrStart))
+ {
+ pvMinVAddr = psLinuxMemArea->uData.sVmalloc.pvVmallocAddress + ui32AreaOffset;
+
+
+ if(pvRangeAddrStart < pvMinVAddr)
+ goto err_blocked;
+
+ pfnInnerCacheOp(pvRangeAddrStart, pvRangeAddrStart + ui32Length);
+ }
+ else
+ {
+
-
- if(pvRangeAddrStart < pvMinVAddr &&
- ui32AreaOffset + ui32Length > ui32AreaLength)
- goto err_blocked;
+
+ pvMinVAddr = FindMMapBaseVAddr(psMMapOffsetStructList,
+ pvRangeAddrStart, ui32Length);
+ if(!pvMinVAddr)
+ goto err_blocked;
+
+ pfnInnerCacheOp(pvRangeAddrStart, pvRangeAddrStart + ui32Length);
#if defined(CONFIG_OUTER_CACHE)
+
+ pvRangeAddrStart = psLinuxMemArea->uData.sVmalloc.pvVmallocAddress +
+ (ui32AreaOffset & PAGE_MASK) + (pvRangeAddrStart - pvMinVAddr);
+ }
+
pfnMemAreaToPhys = VMallocAreaToPhys;
+#else
+ }
#endif
break;
}
case LINUX_MEM_AREA_EXTERNAL_KV:
{
-
+
if (psLinuxMemArea->uData.sExternalKV.bPhysContig == IMG_TRUE)
{
PVR_DPF((PVR_DBG_WARNING, "%s: Attempt to flush contiguous external memory", __func__));
@@ -2709,7 +2736,7 @@ IMG_BOOL CheckExecuteCacheOp(IMG_HANDLE hOSMemHandle,
goto err_blocked;
}
-
+
if (psLinuxMemArea->uData.sExternalKV.pvExternalKV != IMG_NULL)
{
PVR_DPF((PVR_DBG_WARNING, "%s: Attempt to flush external memory with a kernel virtual address", __func__));
@@ -2724,6 +2751,8 @@ IMG_BOOL CheckExecuteCacheOp(IMG_HANDLE hOSMemHandle,
if(!pvMinVAddr)
goto err_blocked;
+ pfnInnerCacheOp(pvRangeAddrStart, pvRangeAddrStart + ui32Length);
+
#if defined(CONFIG_OUTER_CACHE)
ui32PageNumOffset = ((ui32AreaOffset & PAGE_MASK) + (pvRangeAddrStart - pvMinVAddr)) >> PAGE_SHIFT;
pfnMemAreaToPhys = ExternalKVAreaToPhys;
@@ -2738,6 +2767,8 @@ IMG_BOOL CheckExecuteCacheOp(IMG_HANDLE hOSMemHandle,
if(!pvMinVAddr)
goto err_blocked;
+ pfnInnerCacheOp(pvRangeAddrStart, pvRangeAddrStart + ui32Length);
+
#if defined(CONFIG_OUTER_CACHE)
ui32PageNumOffset = ((ui32AreaOffset & PAGE_MASK) + (pvRangeAddrStart - pvMinVAddr)) >> PAGE_SHIFT;
pfnMemAreaToPhys = AllocPagesAreaToPhys;
@@ -2749,12 +2780,10 @@ IMG_BOOL CheckExecuteCacheOp(IMG_HANDLE hOSMemHandle,
PVR_DBG_BREAK;
}
-
- pfnInnerCacheOp(pvRangeAddrStart, pvRangeAddrStart + ui32Length);
-
#if defined(CONFIG_OUTER_CACHE)
+ PVR_ASSERT(pfnMemAreaToPhys != IMG_NULL);
+
- if (pfnMemAreaToPhys != IMG_NULL)
{
unsigned long ulStart, ulEnd, ulLength, ulStartOffset, ulEndOffset;
IMG_UINT32 i, ui32NumPages;
@@ -2782,10 +2811,6 @@ IMG_BOOL CheckExecuteCacheOp(IMG_HANDLE hOSMemHandle,
pfnOuterCacheOp(ulStart, ulEnd);
}
}
- else
- {
- PVR_DBG_BREAK;
- }
#endif
return IMG_TRUE;
@@ -2797,6 +2822,7 @@ err_blocked:
psLinuxMemArea->eAreaType));
return IMG_FALSE;
}
+
#endif
#if defined(__i386__)
@@ -2839,7 +2865,7 @@ IMG_BOOL OSFlushCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
IMG_VOID *pvRangeAddrStart,
IMG_UINT32 ui32Length)
{
-
+
return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length,
x86_flush_cache_range, IMG_NULL);
}
@@ -2848,7 +2874,7 @@ IMG_BOOL OSCleanCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
IMG_VOID *pvRangeAddrStart,
IMG_UINT32 ui32Length)
{
-
+
return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length,
x86_flush_cache_range, IMG_NULL);
}
@@ -2857,12 +2883,12 @@ IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
IMG_VOID *pvRangeAddrStart,
IMG_UINT32 ui32Length)
{
-
+
return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length,
x86_flush_cache_range, IMG_NULL);
}
-#else
+#else
#if defined(__arm__)
@@ -2913,10 +2939,9 @@ IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
dmac_inv_range, outer_inv_range);
}
-#else
+#else
#if defined(__mips__)
-
IMG_VOID OSCleanCPUCacheKM(IMG_VOID)
{
@@ -2953,14 +2978,13 @@ IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
return IMG_TRUE;
}
-
#else
#error "Implement CPU cache flush/clean/invalidate primitives for this CPU!"
-#endif
+#endif
-#endif
+#endif
#endif
@@ -2971,7 +2995,7 @@ PVRSRV_ERROR PVROSFuncInit(IMG_VOID)
psTimerWorkQueue = create_workqueue("pvr_timer");
if (psTimerWorkQueue == NULL)
{
- PVR_DPF((PVR_DBG_ERROR, "%s: couldn't create timer workqueue", __FUNCTION__));
+ PVR_DPF((PVR_DBG_ERROR, "%s: couldn't create timer workqueue", __FUNCTION__));
return PVRSRV_ERROR_UNABLE_TO_CREATE_THREAD;
}
diff --git a/drivers/gpu/pvr/osfunc.h b/drivers/gpu/pvr/osfunc.h
index 8ffbea6..dc209a0 100644
--- a/drivers/gpu/pvr/osfunc.h
+++ b/drivers/gpu/pvr/osfunc.h
@@ -444,7 +444,15 @@ IMG_BOOL OSIsResourceLocked(PVRSRV_RESOURCE *psResource, IMG_UINT32 ui32ID);
PVRSRV_ERROR OSCreateResource(PVRSRV_RESOURCE *psResource);
PVRSRV_ERROR OSDestroyResource(PVRSRV_RESOURCE *psResource);
IMG_VOID OSBreakResourceLock(PVRSRV_RESOURCE *psResource, IMG_UINT32 ui32ID);
+
+
+
IMG_VOID OSWaitus(IMG_UINT32 ui32Timeus);
+
+
+IMG_VOID OSSleepms(IMG_UINT32 ui32Timems);
+
+
IMG_VOID OSReleaseThreadQuanta(IMG_VOID);
IMG_UINT32 OSPCIReadDword(IMG_UINT32 ui32Bus, IMG_UINT32 ui32Dev, IMG_UINT32 ui32Func, IMG_UINT32 ui32Reg);
IMG_VOID OSPCIWriteDword(IMG_UINT32 ui32Bus, IMG_UINT32 ui32Dev, IMG_UINT32 ui32Func, IMG_UINT32 ui32Reg, IMG_UINT32 ui32Value);
@@ -468,7 +476,7 @@ typedef enum _HOST_PCI_INIT_FLAGS_
{
HOST_PCI_INIT_FLAG_BUS_MASTER = 0x00000001,
HOST_PCI_INIT_FLAG_MSI = 0x00000002,
- HOST_PCI_INIT_FLAG_FORCE_I32 = 0x7fffffff
+ HOST_PCI_INIT_FLAG_FORCE_I32 = 0x7fffffff
} HOST_PCI_INIT_FLAGS;
struct _PVRSRV_PCI_DEV_OPAQUE_STRUCT_;
diff --git a/drivers/gpu/pvr/pvrsrv.c b/drivers/gpu/pvr/pvrsrv.c
index 6e19974..5862fb9 100644
--- a/drivers/gpu/pvr/pvrsrv.c
+++ b/drivers/gpu/pvr/pvrsrv.c
@@ -613,32 +613,44 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVDeinitialiseDevice(IMG_UINT32 ui32DevIndex)
IMG_EXPORT
-PVRSRV_ERROR IMG_CALLCONV PollForValueKM (volatile IMG_UINT32* pui32LinMemAddr,
- IMG_UINT32 ui32Value,
- IMG_UINT32 ui32Mask,
- IMG_UINT32 ui32Waitus,
- IMG_UINT32 ui32Tries)
+PVRSRV_ERROR IMG_CALLCONV PollForValueKM (volatile IMG_UINT32* pui32LinMemAddr,
+ IMG_UINT32 ui32Value,
+ IMG_UINT32 ui32Mask,
+ IMG_UINT32 ui32Timeoutus,
+ IMG_UINT32 ui32PollPeriodus,
+ IMG_BOOL bAllowPreemption)
{
{
- IMG_UINT32 ui32ActualValue = 0xFFFFFFFFU;
- IMG_UINT32 uiMaxTime = ui32Tries * ui32Waitus;
+ IMG_UINT32 ui32ActualValue = 0xFFFFFFFFU;
-
- LOOP_UNTIL_TIMEOUT(uiMaxTime)
+ if (bAllowPreemption)
+ {
+ PVR_ASSERT(ui32PollPeriodus >= 1000);
+ }
+
+
+ LOOP_UNTIL_TIMEOUT(ui32Timeoutus)
{
ui32ActualValue = (*pui32LinMemAddr & ui32Mask);
if(ui32ActualValue == ui32Value)
{
return PVRSRV_OK;
}
- OSWaitus(ui32Waitus);
+
+ if (bAllowPreemption)
+ {
+ OSSleepms(ui32PollPeriodus / 1000);
+ }
+ else
+ {
+ OSWaitus(ui32PollPeriodus);
+ }
} END_LOOP_UNTIL_TIMEOUT();
-
+
PVR_DPF((PVR_DBG_ERROR,"PollForValueKM: Timeout. Expected 0x%x but found 0x%x (mask 0x%x).",
ui32Value, ui32ActualValue, ui32Mask));
}
-
return PVRSRV_ERROR_TIMEOUT;
}
@@ -654,7 +666,7 @@ static IMG_VOID PVRSRVGetMiscInfoKM_RA_GetStats_ForEachVaCb(BM_HEAP *psBMHeap, v
pui32StrLen = va_arg(va, IMG_UINT32*);
ui32Mode = va_arg(va, IMG_UINT32);
-
+
switch(ui32Mode)
{
case PVRSRV_MISC_INFO_MEMSTATS_PRESENT:
diff --git a/drivers/gpu/pvr/pvrversion.h b/drivers/gpu/pvr/pvrversion.h
index 4a47ca2..5a431d5 100644
--- a/drivers/gpu/pvr/pvrversion.h
+++ b/drivers/gpu/pvr/pvrversion.h
@@ -30,8 +30,8 @@
#define PVRVERSION_MAJ 1
#define PVRVERSION_MIN 6
#define PVRVERSION_BRANCH 16
-#define PVRVERSION_BUILD 3924
-#define PVRVERSION_STRING "1.6.16.3924"
+#define PVRVERSION_BUILD 4061
+#define PVRVERSION_STRING "1.6.16.4061"
#define PVRVERSION_FILE "eurasiacon.pj"
#endif
diff --git a/drivers/gpu/pvr/queue.c b/drivers/gpu/pvr/queue.c
index 5a3a144..83185f3 100644
--- a/drivers/gpu/pvr/queue.c
+++ b/drivers/gpu/pvr/queue.c
@@ -342,7 +342,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVDestroyCommandQueueKM(PVRSRV_QUEUE_INFO *psQueue
bTimeout = IMG_FALSE;
break;
}
- OSWaitus(MAX_HW_TIME_US/WAIT_TRY_COUNT);
+ OSSleepms(1);
} END_LOOP_UNTIL_TIMEOUT();
if (bTimeout)
@@ -460,7 +460,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetQueueSpaceKM(PVRSRV_QUEUE_INFO *psQueue,
bTimeout = IMG_FALSE;
break;
}
- OSWaitus(MAX_HW_TIME_US/WAIT_TRY_COUNT);
+ OSSleepms(1);
} END_LOOP_UNTIL_TIMEOUT();
if (bTimeout == IMG_TRUE)
@@ -733,14 +733,11 @@ PVRSRV_ERROR PVRSRVProcessCommand(SYS_DATA *psSysData,
psCommand->ui32DataSize,
psCommand->pvData) == IMG_FALSE)
{
-
-
psCmdCompleteData->bInUse = IMG_FALSE;
eError = PVRSRV_ERROR_CMD_NOT_PROCESSED;
}
-
psDeviceCommandData[psCommand->CommandType].ui32CCBOffset = (ui32CCBOffset + 1) % DC_NUM_COMMANDS_PER_TYPE;
return eError;
@@ -822,10 +819,7 @@ PVRSRV_ERROR PVRSRVProcessQueues(IMG_UINT32 ui32CallerID,
UPDATE_QUEUE_ROFF(psQueue, psCommand->ui32CmdSize)
- if (bFlush)
- {
- continue;
- }
+ continue;
}
break;
@@ -972,7 +966,7 @@ PVRSRV_ERROR PVRSRVRegisterCmdProcListKM(IMG_UINT32 ui32DevIndex,
{
psDeviceCommandData[ui32CmdTypeCounter].pfnCmdProc = ppfnCmdProcList[ui32CmdTypeCounter];
psDeviceCommandData[ui32CmdTypeCounter].ui32CCBOffset = 0;
-
+
for (ui32CmdCounter = 0; ui32CmdCounter < DC_NUM_COMMANDS_PER_TYPE; ui32CmdCounter++)
{
@@ -1014,14 +1008,14 @@ PVRSRV_ERROR PVRSRVRegisterCmdProcListKM(IMG_UINT32 ui32DevIndex,
ErrorExit:
-
- if (PVRSRVRemoveCmdProcListKM(ui32DevIndex, ui32CmdCount) != PVRSRV_OK)
- {
- PVR_DPF((PVR_DBG_ERROR,
- "PVRSRVRegisterCmdProcListKM: Failed to clean up after error, device 0x%x",
- ui32DevIndex));
- }
+
+ if (PVRSRVRemoveCmdProcListKM(ui32DevIndex, ui32CmdCount) != PVRSRV_OK)
+ {
+ PVR_DPF((PVR_DBG_ERROR,
+ "PVRSRVRegisterCmdProcListKM: Failed to clean up after error, device 0x%x",
+ ui32DevIndex));
+ }
return eError;
}
@@ -1037,7 +1031,7 @@ PVRSRV_ERROR PVRSRVRemoveCmdProcListKM(IMG_UINT32 ui32DevIndex,
COMMAND_COMPLETE_DATA *psCmdCompleteData;
IMG_SIZE_T ui32AllocSize;
-
+
if(ui32DevIndex >= SYS_DEVICE_COUNT)
{
PVR_DPF((PVR_DBG_ERROR,
@@ -1046,7 +1040,7 @@ PVRSRV_ERROR PVRSRVRemoveCmdProcListKM(IMG_UINT32 ui32DevIndex,
return PVRSRV_ERROR_INVALID_PARAMS;
}
-
+
SysAcquireData(&psSysData);
psDeviceCommandData = psSysData->apsDeviceCommandData[ui32DevIndex];
@@ -1068,7 +1062,7 @@ PVRSRV_ERROR PVRSRVRemoveCmdProcListKM(IMG_UINT32 ui32DevIndex,
}
}
-
+
ui32AllocSize = ui32CmdCount * sizeof(*psDeviceCommandData);
OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP, ui32AllocSize, psDeviceCommandData, IMG_NULL);
psSysData->apsDeviceCommandData[ui32DevIndex] = IMG_NULL;
diff --git a/drivers/gpu/pvr/servicesext.h b/drivers/gpu/pvr/servicesext.h
index 2f81b11..6f72705 100644
--- a/drivers/gpu/pvr/servicesext.h
+++ b/drivers/gpu/pvr/servicesext.h
@@ -434,62 +434,62 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
PVRSRV_PIXEL_FORMAT_G16R16 = 101,
- PVRSRV_PIXEL_FORMAT_G16R16F = 102,
- PVRSRV_PIXEL_FORMAT_G16R16_UINT = 103,
- PVRSRV_PIXEL_FORMAT_G16R16_UNORM = 104,
- PVRSRV_PIXEL_FORMAT_G16R16_SINT = 105,
- PVRSRV_PIXEL_FORMAT_G16R16_SNORM = 106,
+ PVRSRV_PIXEL_FORMAT_G16R16F = 102,
+ PVRSRV_PIXEL_FORMAT_G16R16_UINT = 103,
+ PVRSRV_PIXEL_FORMAT_G16R16_UNORM = 104,
+ PVRSRV_PIXEL_FORMAT_G16R16_SINT = 105,
+ PVRSRV_PIXEL_FORMAT_G16R16_SNORM = 106,
-
- PVRSRV_PIXEL_FORMAT_R16 = 107,
- PVRSRV_PIXEL_FORMAT_R16F = 108,
- PVRSRV_PIXEL_FORMAT_R16_UINT = 109,
- PVRSRV_PIXEL_FORMAT_R16_UNORM = 110,
- PVRSRV_PIXEL_FORMAT_R16_SINT = 111,
- PVRSRV_PIXEL_FORMAT_R16_SNORM = 112,
-
- PVRSRV_PIXEL_FORMAT_X8R8G8B8 = 113,
- PVRSRV_PIXEL_FORMAT_X8R8G8B8_UNORM = 114,
- PVRSRV_PIXEL_FORMAT_X8R8G8B8_UNORM_SRGB = 115,
+ PVRSRV_PIXEL_FORMAT_R16 = 107,
+ PVRSRV_PIXEL_FORMAT_R16F = 108,
+ PVRSRV_PIXEL_FORMAT_R16_UINT = 109,
+ PVRSRV_PIXEL_FORMAT_R16_UNORM = 110,
+ PVRSRV_PIXEL_FORMAT_R16_SINT = 111,
+ PVRSRV_PIXEL_FORMAT_R16_SNORM = 112,
- PVRSRV_PIXEL_FORMAT_A8R8G8B8 = 116,
- PVRSRV_PIXEL_FORMAT_A8R8G8B8_UNORM = 117,
- PVRSRV_PIXEL_FORMAT_A8R8G8B8_UNORM_SRGB = 118,
- PVRSRV_PIXEL_FORMAT_A8B8G8R8 = 119,
- PVRSRV_PIXEL_FORMAT_A8B8G8R8_UINT = 120,
- PVRSRV_PIXEL_FORMAT_A8B8G8R8_UNORM = 121,
- PVRSRV_PIXEL_FORMAT_A8B8G8R8_UNORM_SRGB = 122,
- PVRSRV_PIXEL_FORMAT_A8B8G8R8_SINT = 123,
- PVRSRV_PIXEL_FORMAT_A8B8G8R8_SNORM = 124,
+ PVRSRV_PIXEL_FORMAT_X8R8G8B8 = 113,
+ PVRSRV_PIXEL_FORMAT_X8R8G8B8_UNORM = 114,
+ PVRSRV_PIXEL_FORMAT_X8R8G8B8_UNORM_SRGB = 115,
-
- PVRSRV_PIXEL_FORMAT_G8R8 = 125,
- PVRSRV_PIXEL_FORMAT_G8R8_UINT = 126,
- PVRSRV_PIXEL_FORMAT_G8R8_UNORM = 127,
- PVRSRV_PIXEL_FORMAT_G8R8_SINT = 128,
- PVRSRV_PIXEL_FORMAT_G8R8_SNORM = 129,
+ PVRSRV_PIXEL_FORMAT_A8R8G8B8 = 116,
+ PVRSRV_PIXEL_FORMAT_A8R8G8B8_UNORM = 117,
+ PVRSRV_PIXEL_FORMAT_A8R8G8B8_UNORM_SRGB = 118,
-
- PVRSRV_PIXEL_FORMAT_A8 = 130,
- PVRSRV_PIXEL_FORMAT_R8 = 131,
- PVRSRV_PIXEL_FORMAT_R8_UINT = 132,
- PVRSRV_PIXEL_FORMAT_R8_UNORM = 133,
- PVRSRV_PIXEL_FORMAT_R8_SINT = 134,
- PVRSRV_PIXEL_FORMAT_R8_SNORM = 135,
+ PVRSRV_PIXEL_FORMAT_A8B8G8R8 = 119,
+ PVRSRV_PIXEL_FORMAT_A8B8G8R8_UINT = 120,
+ PVRSRV_PIXEL_FORMAT_A8B8G8R8_UNORM = 121,
+ PVRSRV_PIXEL_FORMAT_A8B8G8R8_UNORM_SRGB = 122,
+ PVRSRV_PIXEL_FORMAT_A8B8G8R8_SINT = 123,
+ PVRSRV_PIXEL_FORMAT_A8B8G8R8_SNORM = 124,
-
- PVRSRV_PIXEL_FORMAT_A2B10G10R10 = 136,
- PVRSRV_PIXEL_FORMAT_A2B10G10R10_UNORM = 137,
- PVRSRV_PIXEL_FORMAT_A2B10G10R10_UINT = 138,
-
- PVRSRV_PIXEL_FORMAT_B10G11R11 = 139,
- PVRSRV_PIXEL_FORMAT_B10G11R11F = 140,
+ PVRSRV_PIXEL_FORMAT_G8R8 = 125,
+ PVRSRV_PIXEL_FORMAT_G8R8_UINT = 126,
+ PVRSRV_PIXEL_FORMAT_G8R8_UNORM = 127,
+ PVRSRV_PIXEL_FORMAT_G8R8_SINT = 128,
+ PVRSRV_PIXEL_FORMAT_G8R8_SNORM = 129,
-
- PVRSRV_PIXEL_FORMAT_X24G8R32 = 141,
+
+ PVRSRV_PIXEL_FORMAT_A8 = 130,
+ PVRSRV_PIXEL_FORMAT_R8 = 131,
+ PVRSRV_PIXEL_FORMAT_R8_UINT = 132,
+ PVRSRV_PIXEL_FORMAT_R8_UNORM = 133,
+ PVRSRV_PIXEL_FORMAT_R8_SINT = 134,
+ PVRSRV_PIXEL_FORMAT_R8_SNORM = 135,
+
+
+ PVRSRV_PIXEL_FORMAT_A2B10G10R10 = 136,
+ PVRSRV_PIXEL_FORMAT_A2B10G10R10_UNORM = 137,
+ PVRSRV_PIXEL_FORMAT_A2B10G10R10_UINT = 138,
+
+
+ PVRSRV_PIXEL_FORMAT_B10G11R11 = 139,
+ PVRSRV_PIXEL_FORMAT_B10G11R11F = 140,
+
+
+ PVRSRV_PIXEL_FORMAT_X24G8R32 = 141,
PVRSRV_PIXEL_FORMAT_G8R24 = 142,
PVRSRV_PIXEL_FORMAT_X8R24 = 143,
PVRSRV_PIXEL_FORMAT_E5B9G9R9 = 144,
@@ -511,20 +511,20 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
PVRSRV_PIXEL_FORMAT_RESERVED19 = 159,
PVRSRV_PIXEL_FORMAT_RESERVED20 = 160,
-
- PVRSRV_PIXEL_FORMAT_UBYTE4 = 161,
- PVRSRV_PIXEL_FORMAT_SHORT4 = 162,
- PVRSRV_PIXEL_FORMAT_SHORT4N = 163,
- PVRSRV_PIXEL_FORMAT_USHORT4N = 164,
- PVRSRV_PIXEL_FORMAT_SHORT2N = 165,
- PVRSRV_PIXEL_FORMAT_SHORT2 = 166,
- PVRSRV_PIXEL_FORMAT_USHORT2N = 167,
- PVRSRV_PIXEL_FORMAT_UDEC3 = 168,
- PVRSRV_PIXEL_FORMAT_DEC3N = 169,
- PVRSRV_PIXEL_FORMAT_F16_2 = 170,
- PVRSRV_PIXEL_FORMAT_F16_4 = 171,
-
+ PVRSRV_PIXEL_FORMAT_UBYTE4 = 161,
+ PVRSRV_PIXEL_FORMAT_SHORT4 = 162,
+ PVRSRV_PIXEL_FORMAT_SHORT4N = 163,
+ PVRSRV_PIXEL_FORMAT_USHORT4N = 164,
+ PVRSRV_PIXEL_FORMAT_SHORT2N = 165,
+ PVRSRV_PIXEL_FORMAT_SHORT2 = 166,
+ PVRSRV_PIXEL_FORMAT_USHORT2N = 167,
+ PVRSRV_PIXEL_FORMAT_UDEC3 = 168,
+ PVRSRV_PIXEL_FORMAT_DEC3N = 169,
+ PVRSRV_PIXEL_FORMAT_F16_2 = 170,
+ PVRSRV_PIXEL_FORMAT_F16_4 = 171,
+
+
PVRSRV_PIXEL_FORMAT_L_F16 = 172,
PVRSRV_PIXEL_FORMAT_L_F16_REP = 173,
PVRSRV_PIXEL_FORMAT_L_F16_A_F16 = 174,
@@ -535,7 +535,7 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
PVRSRV_PIXEL_FORMAT_A_F32 = 178,
PVRSRV_PIXEL_FORMAT_L_F32_A_F32 = 179,
-
+
PVRSRV_PIXEL_FORMAT_PVRTC2 = 180,
PVRSRV_PIXEL_FORMAT_PVRTC4 = 181,
PVRSRV_PIXEL_FORMAT_PVRTCII2 = 182,
@@ -552,7 +552,7 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
PVRSRV_PIXEL_FORMAT_MONO8 = 193,
PVRSRV_PIXEL_FORMAT_MONO16 = 194,
-
+
PVRSRV_PIXEL_FORMAT_C0_YUYV = 195,
PVRSRV_PIXEL_FORMAT_C0_UYVY = 196,
PVRSRV_PIXEL_FORMAT_C0_YVYU = 197,
@@ -562,7 +562,7 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
PVRSRV_PIXEL_FORMAT_C1_YVYU = 201,
PVRSRV_PIXEL_FORMAT_C1_VYUY = 202,
-
+
PVRSRV_PIXEL_FORMAT_C0_YUV420_2P_UV = 203,
PVRSRV_PIXEL_FORMAT_C0_YUV420_2P_VU = 204,
PVRSRV_PIXEL_FORMAT_C0_YUV420_3P = 205,
@@ -573,10 +573,10 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
PVRSRV_PIXEL_FORMAT_A2B10G10R10F = 209,
PVRSRV_PIXEL_FORMAT_B8G8R8_SINT = 210,
PVRSRV_PIXEL_FORMAT_PVRF32SIGNMASK = 211,
-
+
PVRSRV_PIXEL_FORMAT_ABGR4444 = 212,
PVRSRV_PIXEL_FORMAT_ABGR1555 = 213,
- PVRSRV_PIXEL_FORMAT_BGR565 = 214,
+ PVRSRV_PIXEL_FORMAT_BGR565 = 214,
PVRSRV_PIXEL_FORMAT_FORCE_I32 = 0x7fffffff
@@ -612,15 +612,15 @@ typedef enum _PVRSRV_ROTATION_ {
typedef struct _PVRSRV_SYNC_DATA_
{
-
+
IMG_UINT32 ui32WriteOpsPending;
volatile IMG_UINT32 ui32WriteOpsComplete;
-
+
IMG_UINT32 ui32ReadOpsPending;
volatile IMG_UINT32 ui32ReadOpsComplete;
-
+
IMG_UINT32 ui32LastOpDumpVal;
IMG_UINT32 ui32LastReadOpDumpVal;
@@ -628,22 +628,22 @@ typedef struct _PVRSRV_SYNC_DATA_
typedef struct _PVRSRV_CLIENT_SYNC_INFO_
{
-
+
PVRSRV_SYNC_DATA *psSyncData;
-
-
+
+
IMG_DEV_VIRTADDR sWriteOpsCompleteDevVAddr;
-
+
IMG_DEV_VIRTADDR sReadOpsCompleteDevVAddr;
-
+
IMG_HANDLE hMappingInfo;
-
+
IMG_HANDLE hKernelSyncInfo;
} PVRSRV_CLIENT_SYNC_INFO, *PPVRSRV_CLIENT_SYNC_INFO;
@@ -651,7 +651,7 @@ typedef struct _PVRSRV_CLIENT_SYNC_INFO_
typedef struct PVRSRV_RESOURCE_TAG
{
volatile IMG_UINT32 ui32Lock;
- IMG_UINT32 ui32ID;
+ IMG_UINT32 ui32ID;
}PVRSRV_RESOURCE;
typedef PVRSRV_RESOURCE PVRSRV_RES_HANDLE;
@@ -700,52 +700,52 @@ typedef struct DISPLAY_DIMS_TAG
typedef struct DISPLAY_FORMAT_TAG
{
-
+
PVRSRV_PIXEL_FORMAT pixelformat;
} DISPLAY_FORMAT;
typedef struct DISPLAY_SURF_ATTRIBUTES_TAG
{
-
+
PVRSRV_PIXEL_FORMAT pixelformat;
-
+
DISPLAY_DIMS sDims;
} DISPLAY_SURF_ATTRIBUTES;
typedef struct DISPLAY_MODE_INFO_TAG
{
-
+
PVRSRV_PIXEL_FORMAT pixelformat;
-
+
DISPLAY_DIMS sDims;
-
+
IMG_UINT32 ui32RefreshHZ;
-
+
IMG_UINT32 ui32OEMFlags;
} DISPLAY_MODE_INFO;
-#define MAX_DISPLAY_NAME_SIZE (50)
+#define MAX_DISPLAY_NAME_SIZE (50)
typedef struct DISPLAY_INFO_TAG
{
-
+
IMG_UINT32 ui32MaxSwapChains;
-
+
IMG_UINT32 ui32MaxSwapChainBuffers;
-
+
IMG_UINT32 ui32MinSwapInterval;
-
+
IMG_UINT32 ui32MaxSwapInterval;
-
+
IMG_UINT32 ui32PhysicalWidthmm;
IMG_UINT32 ui32PhysicalHeightmm;
-
+
IMG_CHAR szDisplayName[MAX_DISPLAY_NAME_SIZE];
#if defined(SUPPORT_HW_CURSOR)
-
+
IMG_UINT16 ui32CursorWidth;
IMG_UINT16 ui32CursorHeight;
#endif
@@ -754,9 +754,9 @@ typedef struct DISPLAY_INFO_TAG
typedef struct ACCESS_INFO_TAG
{
IMG_UINT32 ui32Size;
- IMG_UINT32 ui32FBPhysBaseAddress;
- IMG_UINT32 ui32FBMemAvailable;
- IMG_UINT32 ui32SysPhysBaseAddress;
+ IMG_UINT32 ui32FBPhysBaseAddress;
+ IMG_UINT32 ui32FBMemAvailable;
+ IMG_UINT32 ui32SysPhysBaseAddress;
IMG_UINT32 ui32SysSize;
IMG_UINT32 ui32DevIRQ;
}ACCESS_INFO;
@@ -769,11 +769,11 @@ typedef struct PVRSRV_CURSOR_SHAPE_TAG
IMG_INT16 i16XHot;
IMG_INT16 i16YHot;
-
- IMG_VOID* pvMask;
- IMG_INT16 i16MaskByteStride;
-
+ IMG_VOID* pvMask;
+ IMG_INT16 i16MaskByteStride;
+
+
IMG_VOID* pvColour;
IMG_INT16 i16ColourByteStride;
PVRSRV_PIXEL_FORMAT eColourPixelFormat;
@@ -786,24 +786,34 @@ typedef struct PVRSRV_CURSOR_SHAPE_TAG
typedef struct PVRSRV_CURSOR_INFO_TAG
{
-
+
IMG_UINT32 ui32Flags;
-
+
IMG_BOOL bVisible;
-
+
IMG_INT16 i16XPos;
IMG_INT16 i16YPos;
-
+
PVRSRV_CURSOR_SHAPE sCursorShape;
-
+
IMG_UINT32 ui32Rotation;
} PVRSRV_CURSOR_INFO;
+#if defined(PDUMP_SUSPEND_IS_PER_THREAD)
+typedef struct {
+ IMG_UINT32 threadId;
+ int suspendCount;
+} PVRSRV_THREAD_SUSPEND_COUNT;
+
+#define PVRSRV_PDUMP_SUSPEND_Q_NAME "PVRSRVPDumpSuspendMsgQ"
+#define PVRSRV_PDUMP_SUSPEND_Q_LENGTH 8
+
+#endif
typedef struct _PVRSRV_REGISTRY_INFO_
{
@@ -825,11 +835,11 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVWriteRegistryString (PPVRSRV_REGISTRY_INFO psReg
#define PVRSRV_BC_FLAGS_YUVCSC_BT601 (0 << 1)
#define PVRSRV_BC_FLAGS_YUVCSC_BT709 (1 << 1)
-#define MAX_BUFFER_DEVICE_NAME_SIZE (50)
+#define MAX_BUFFER_DEVICE_NAME_SIZE (50)
typedef struct BUFFER_INFO_TAG
{
- IMG_UINT32 ui32BufferCount;
+ IMG_UINT32 ui32BufferCount;
IMG_UINT32 ui32BufferDeviceID;
PVRSRV_PIXEL_FORMAT pixelformat;
IMG_UINT32 ui32ByteStride;
@@ -847,4 +857,4 @@ typedef enum _OVERLAY_DEINTERLACE_MODE_
BOB_EVEN_NONINTERLEAVED
} OVERLAY_DEINTERLACE_MODE;
-#endif
+#endif
diff --git a/drivers/gpu/pvr/sgx/sgxconfig.h b/drivers/gpu/pvr/sgx/sgxconfig.h
index a0ca3e9..6d9d077 100644
--- a/drivers/gpu/pvr/sgx/sgxconfig.h
+++ b/drivers/gpu/pvr/sgx/sgxconfig.h
@@ -82,19 +82,24 @@
#define SGX_VERTEXSHADER_HEAP_BASE 0xFE000000
#define SGX_VERTEXSHADER_HEAP_SIZE (0x02000000-0x00001000)
-
+
#define SGX_CORE_IDENTIFIED
-#endif
+#endif
#if SGX_FEATURE_ADDRESS_SPACE_SIZE == 28
- #if defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP)
+
+#if defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP)
#define SGX_GENERAL_MAPPING_HEAP_BASE 0x00001000
#define SGX_GENERAL_MAPPING_HEAP_SIZE (0x01800000-0x00001000-0x00001000)
- #endif
-
+
#define SGX_GENERAL_HEAP_BASE 0x01800000
#define SGX_GENERAL_HEAP_SIZE (0x07000000-0x00001000)
+#else
+ #define SGX_GENERAL_HEAP_BASE 0x00001000
+ #define SGX_GENERAL_HEAP_SIZE (0x08800000-0x00001000-0x00001000)
+#endif
+
#define SGX_3DPARAMETERS_HEAP_BASE 0x08800000
#define SGX_3DPARAMETERS_HEAP_SIZE (0x04000000-0x00001000)
@@ -122,10 +127,10 @@
#define SGX_VERTEXSHADER_HEAP_BASE 0x0FC00000
#define SGX_VERTEXSHADER_HEAP_SIZE (0x00200000-0x00001000)
-
+
#define SGX_CORE_IDENTIFIED
-#endif
+#endif
#if !defined(SGX_CORE_IDENTIFIED)
#error "sgxconfig.h: ERROR: unspecified SGX Core version"
diff --git a/drivers/gpu/pvr/sgx/sgxinit.c b/drivers/gpu/pvr/sgx/sgxinit.c
index f822eb8..3872102 100644
--- a/drivers/gpu/pvr/sgx/sgxinit.c
+++ b/drivers/gpu/pvr/sgx/sgxinit.c
@@ -379,18 +379,19 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
PDUMP_FLAGS_CONTINUOUS,
MAKEUNIQUETAG(psDevInfo->psKernelCCBEventKickerMemInfo));
PDUMPREG(SGX_PDUMPREG_NAME, SGX_MP_CORE_SELECT(EUR_CR_EVENT_KICK, 0), EUR_CR_EVENT_KICK_NOW_MASK);
-#endif
+#endif
}
-#endif
+#endif
#if !defined(NO_HARDWARE)
-
+
if (PollForValueKM(&psSGXHostCtl->ui32InitStatus,
PVRSRV_USSE_EDM_INIT_COMPLETE,
PVRSRV_USSE_EDM_INIT_COMPLETE,
+ MAX_HW_TIME_US,
MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
+ IMG_FALSE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "SGXInitialise: Wait for uKernel initialisation failed"));
#if !defined(FIX_HW_BRN_23281)
@@ -398,7 +399,7 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
#endif
return PVRSRV_ERROR_RETRY;
}
-#endif
+#endif
#if defined(PDUMP)
PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
@@ -410,19 +411,19 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
PDUMP_POLL_OPERATOR_EQUAL,
PDUMP_FLAGS_CONTINUOUS,
MAKEUNIQUETAG(psSGXHostCtlMemInfo));
-#endif
+#endif
#if defined(FIX_HW_BRN_22997) && defined(FIX_HW_BRN_23030) && defined(SGX_FEATURE_HOST_PORT)
-
+
WorkaroundBRN22997ReadHostPort(psDevInfo);
-#endif
+#endif
PVR_ASSERT(psDevInfo->psKernelCCBCtl->ui32ReadOffset == psDevInfo->psKernelCCBCtl->ui32WriteOffset);
bFirstTime = IMG_FALSE;
-
+
return PVRSRV_OK;
}
@@ -432,7 +433,7 @@ PVRSRV_ERROR SGXDeinitialise(IMG_HANDLE hDevCookie)
PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *) hDevCookie;
PVRSRV_ERROR eError;
-
+
if (psDevInfo->pvRegsBaseKM == IMG_NULL)
{
return PVRSRV_OK;
@@ -460,12 +461,12 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode)
DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap = psDeviceNode->sDevMemoryInfo.psDeviceMemoryHeap;
PVRSRV_ERROR eError;
-
+
PDUMPCOMMENT("SGX Core Version Information: %s", SGX_CORE_FRIENDLY_NAME);
-
+
#if defined(SGX_FEATURE_MP)
PDUMPCOMMENT("SGX Multi-processor: %d cores", SGX_FEATURE_MP_CORE_COUNT);
- #endif
+ #endif
#if (SGX_CORE_REV == 0)
PDUMPCOMMENT("SGX Core Revision Information: head RTL");
@@ -477,8 +478,8 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode)
PDUMPCOMMENT("SGX System Level Cache is present\r\n");
#if defined(SGX_BYPASS_SYSTEM_CACHE)
PDUMPCOMMENT("SGX System Level Cache is bypassed\r\n");
- #endif
- #endif
+ #endif
+ #endif
PDUMPCOMMENT("SGX Initialisation Part 1");
@@ -1027,10 +1028,10 @@ IMG_VOID HWRecoveryResetSGX (PVRSRV_DEVICE_NODE *psDeviceNode,
SGXDumpDebugInfo(psDeviceNode->pvDevice, IMG_TRUE);
-
+
PDUMPSUSPEND();
-
+
#if defined(FIX_HW_BRN_23281)
for (eError = PVRSRV_ERROR_RETRY; eError == PVRSRV_ERROR_RETRY;)
@@ -1044,19 +1045,19 @@ IMG_VOID HWRecoveryResetSGX (PVRSRV_DEVICE_NODE *psDeviceNode,
PVR_DPF((PVR_DBG_ERROR,"HWRecoveryResetSGX: SGXInitialise failed (%d)", eError));
}
-
+
PDUMPRESUME();
PVRSRVPowerUnlock(ui32CallerID);
-
+
SGXScheduleProcessQueuesKM(psDeviceNode);
-
-
+
+
PVRSRVProcessQueues(ui32CallerID, IMG_TRUE);
}
-#endif
+#endif
#if defined(SUPPORT_HW_RECOVERY)
@@ -1065,7 +1066,7 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
PVRSRV_DEVICE_NODE *psDeviceNode = pvData;
PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
static IMG_UINT32 ui32EDMTasks = 0;
- static IMG_UINT32 ui32LockupCounter = 0;
+ static IMG_UINT32 ui32LockupCounter = 0;
static IMG_UINT32 ui32NumResets = 0;
#if defined(FIX_HW_BRN_31093)
static IMG_BOOL bBRN31093Inval = IMG_FALSE;
@@ -1074,17 +1075,17 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
IMG_BOOL bLockup = IMG_FALSE;
IMG_BOOL bPoweredDown;
-
+
psDevInfo->ui32TimeStamp++;
#if defined(NO_HARDWARE)
bPoweredDown = IMG_TRUE;
#else
bPoweredDown = (SGXIsDevicePowered(psDeviceNode)) ? IMG_FALSE : IMG_TRUE;
-#endif
+#endif
+
+
-
-
if (bPoweredDown)
{
ui32LockupCounter = 0;
@@ -1094,7 +1095,7 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
}
else
{
-
+
ui32CurrentEDMTasks = OSReadHWReg(psDevInfo->pvRegsBaseKM, psDevInfo->ui32EDMTaskReg0);
if (psDevInfo->ui32EDMTaskReg1 != 0)
{
@@ -1156,14 +1157,14 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
{
SGXMKIF_HOST_CTL *psSGXHostCtl = (SGXMKIF_HOST_CTL *)psDevInfo->psSGXHostCtl;
-
+
psSGXHostCtl->ui32HostDetectedLockups ++;
-
+
HWRecoveryResetSGX(psDeviceNode, 0, KERNEL_ID);
}
}
-#endif
+#endif
#if defined(SYS_USING_INTERRUPTS)
@@ -1173,18 +1174,18 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
IMG_BOOL bInterruptProcessed = IMG_FALSE;
-
+
{
IMG_UINT32 ui32EventStatus, ui32EventEnable;
IMG_UINT32 ui32EventClear = 0;
#if defined(SGX_FEATURE_DATA_BREAKPOINTS)
IMG_UINT32 ui32EventStatus2, ui32EventEnable2;
-#endif
+#endif
IMG_UINT32 ui32EventClear2 = 0;
PVRSRV_DEVICE_NODE *psDeviceNode;
PVRSRV_SGXDEV_INFO *psDevInfo;
-
+
if(pvData == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "SGX_ISRHandler: Invalid params\n"));
@@ -1197,18 +1198,18 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
ui32EventStatus = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
ui32EventEnable = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE);
-
+
ui32EventStatus &= ui32EventEnable;
#if defined(SGX_FEATURE_DATA_BREAKPOINTS)
ui32EventStatus2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2);
ui32EventEnable2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE2);
-
+
ui32EventStatus2 &= ui32EventEnable2;
-#endif
+#endif
+
-
if (ui32EventStatus & EUR_CR_EVENT_STATUS_SW_EVENT_MASK)
{
@@ -1225,16 +1226,16 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
{
ui32EventClear2 |= EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK;
}
-#endif
+#endif
if (ui32EventClear || ui32EventClear2)
{
bInterruptProcessed = IMG_TRUE;
-
+
ui32EventClear |= EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK;
-
+
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32EventClear);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32EventClear2);
}
@@ -1265,7 +1266,7 @@ static IMG_VOID SGX_MISRHandler (IMG_VOID *pvData)
SGXTestActivePowerEvent(psDeviceNode, ISR_ID);
}
-#endif
+#endif
@@ -1283,14 +1284,14 @@ PVRSRV_ERROR SGX_AllocMemTilingRange(PVRSRV_DEVICE_NODE *psDeviceNode,
IMG_UINT32 ui32Offset;
IMG_UINT32 ui32Val;
-
+
for(i=0; i<10; i++)
{
if((psDevInfo->ui32MemTilingUsage & (1U << i)) == 0)
{
-
+
psDevInfo->ui32MemTilingUsage |= 1U << i;
-
+
*pui32RangeIndex = i;
goto RangeAllocated;
}
@@ -1310,7 +1311,7 @@ RangeAllocated:
| (((ui32Start>>20) << EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT) & EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK)
| (0x8 << EUR_CR_BIF_TILE0_CFG_SHIFT);
-
+
OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val);
PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val);
@@ -1319,7 +1320,7 @@ RangeAllocated:
ui32Val = (((ui32End>>12) << EUR_CR_BIF_TILE0_ADDR_EXT_MAX_SHIFT) & EUR_CR_BIF_TILE0_ADDR_EXT_MAX_MASK)
| (((ui32Start>>12) << EUR_CR_BIF_TILE0_ADDR_EXT_MIN_SHIFT) & EUR_CR_BIF_TILE0_ADDR_EXT_MIN_MASK);
-
+
OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val);
PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val);
@@ -1349,14 +1350,14 @@ PVRSRV_ERROR SGX_FreeMemTilingRange(PVRSRV_DEVICE_NODE *psDeviceNode,
return PVRSRV_ERROR_INVALID_PARAMS;
}
-
+
psDevInfo->ui32MemTilingUsage &= ~(1<<ui32RangeIndex);
-
+
ui32Offset = EUR_CR_BIF_TILE0 + (ui32RangeIndex<<2);
ui32Val = 0;
-
+
OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val);
PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val);
@@ -1377,12 +1378,12 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
DEVICE_MEMORY_INFO *psDevMemoryInfo;
DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
-
+
psDeviceNode->sDevId.eDeviceType = DEV_DEVICE_TYPE;
psDeviceNode->sDevId.eDeviceClass = DEV_DEVICE_CLASS;
#if defined(PDUMP)
{
-
+
SGX_DEVICE_MAP *psSGXDeviceMemMap;
SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE_SGX,
(IMG_VOID**)&psSGXDeviceMemMap);
@@ -1390,9 +1391,9 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
psDeviceNode->sDevId.pszPDumpDevName = psSGXDeviceMemMap->pszPDumpDevName;
PVR_ASSERT(psDeviceNode->sDevId.pszPDumpDevName != IMG_NULL);
}
-
+
psDeviceNode->sDevId.pszPDumpRegName = SGX_PDUMPREG_NAME;
-#endif
+#endif
psDeviceNode->pfnInitDevice = &DevInitSGXPart1;
psDeviceNode->pfnDeInitDevice = &DevDeInitSGX;
@@ -1402,7 +1403,7 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
psDeviceNode->pfnPDumpInitDevice = &SGXResetPDump;
psDeviceNode->pfnMMUGetContextID = &MMU_GetPDumpContextID;
#endif
-
+
psDeviceNode->pfnMMUInitialise = &MMU_Initialise;
psDeviceNode->pfnMMUFinalise = &MMU_Finalise;
@@ -1422,7 +1423,7 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
#endif
#if defined (SYS_USING_INTERRUPTS)
-
+
psDeviceNode->pfnDeviceISR = SGX_ISRHandler;
psDeviceNode->pfnDeviceMISR = SGX_MISRHandler;
@@ -1433,20 +1434,20 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
psDeviceNode->pfnFreeMemTilingRange = SGX_FreeMemTilingRange;
#endif
-
+
psDeviceNode->pfnDeviceCommandComplete = &SGXCommandComplete;
-
+
psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo;
-
+
psDevMemoryInfo->ui32AddressSpaceSizeLog2 = SGX_FEATURE_ADDRESS_SPACE_SIZE;
-
+
psDevMemoryInfo->ui32Flags = 0;
-
+
if(OSAllocMem( PVRSRV_OS_PAGEABLE_HEAP,
sizeof(DEVICE_MEMORY_HEAP_INFO) * SGX_MAX_HEAP_ID,
(IMG_VOID **)&psDevMemoryInfo->psDeviceMemoryHeap, 0,
@@ -1459,10 +1460,7 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap;
-
-
-
psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_GENERAL_HEAP_ID);
psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_GENERAL_HEAP_BASE;
psDeviceMemoryHeap->ui32HeapSize = SGX_GENERAL_HEAP_SIZE;
@@ -1472,16 +1470,16 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
psDeviceMemoryHeap->pszName = "General";
psDeviceMemoryHeap->pszBSName = "General BS";
psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT;
-
+
psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE;
#if !defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP)
-
+
psDevMemoryInfo->ui32MappingHeapID = (IMG_UINT32)(psDeviceMemoryHeap - psDevMemoryInfo->psDeviceMemoryHeap);
#endif
psDeviceMemoryHeap++;
-
+
psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_TADATA_HEAP_ID);
psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_TADATA_HEAP_BASE;
psDeviceMemoryHeap->ui32HeapSize = SGX_TADATA_HEAP_SIZE;
@@ -1491,12 +1489,12 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
psDeviceMemoryHeap->pszName = "TA Data";
psDeviceMemoryHeap->pszBSName = "TA Data BS";
psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT;
-
+
psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE;
psDeviceMemoryHeap++;
-
+
psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_KERNEL_CODE_HEAP_ID);
psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_KERNEL_CODE_HEAP_BASE;
psDeviceMemoryHeap->ui32HeapSize = SGX_KERNEL_CODE_HEAP_SIZE;
@@ -1989,7 +1987,8 @@ PVRSRV_ERROR SGXGetMiscInfoUkernel(PVRSRV_SGXDEV_INFO *psDevInfo,
SGXMKIF_CMD_GETMISCINFO,
&sCommandData,
KERNEL_ID,
- 0);
+ 0,
+ IMG_FALSE);
if (eError != PVRSRV_OK)
{
@@ -2099,7 +2098,8 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
SGXMKIF_CMD_DATABREAKPOINT,
&sCommandData,
KERNEL_ID,
- 0);
+ 0,
+ IMG_FALSE);
if (eError != PVRSRV_OK)
{
@@ -2480,7 +2480,8 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
SGXMKIF_CMD_SETHWPERFSTATUS,
&sCommandData,
KERNEL_ID,
- 0);
+ 0,
+ IMG_FALSE);
return eError;
}
#endif
diff --git a/drivers/gpu/pvr/sgx/sgxkick.c b/drivers/gpu/pvr/sgx/sgxkick.c
index 8a229c9..581640b 100644
--- a/drivers/gpu/pvr/sgx/sgxkick.c
+++ b/drivers/gpu/pvr/sgx/sgxkick.c
@@ -550,7 +550,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
}
#endif
- eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TA, &psCCBKick->sCommand, KERNEL_ID, 0);
+ eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TA, &psCCBKick->sCommand, KERNEL_ID, 0, psCCBKick->bLastInScene);
if (eError == PVRSRV_ERROR_RETRY)
{
if (psCCBKick->bFirstKickOrResume && psCCBKick->ui32NumDstSyncObjects > 0)
diff --git a/drivers/gpu/pvr/sgx/sgxpower.c b/drivers/gpu/pvr/sgx/sgxpower.c
index aeac6e3..427cb50 100644
--- a/drivers/gpu/pvr/sgx/sgxpower.c
+++ b/drivers/gpu/pvr/sgx/sgxpower.c
@@ -197,8 +197,9 @@ static IMG_VOID SGXPollForClockGating (PVRSRV_SGXDEV_INFO *psDevInfo,
if (PollForValueKM((IMG_UINT32 *)psDevInfo->pvRegsBaseKM + (ui32Register >> 2),
0,
ui32RegisterValue,
+ MAX_HW_TIME_US,
MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
+ IMG_FALSE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXPollForClockGating: %s failed.", pszComment));
PVR_DBG_BREAK;
@@ -251,7 +252,7 @@ PVRSRV_ERROR SGXPrePowerState (IMG_HANDLE hDevHandle,
sCommand.ui32Data[1] = ui32PowerCmd;
- eError = SGXScheduleCCBCommand(psDevInfo, SGXMKIF_CMD_POWER, &sCommand, KERNEL_ID, 0);
+ eError = SGXScheduleCCBCommand(psDevInfo, SGXMKIF_CMD_POWER, &sCommand, KERNEL_ID, 0, IMG_FALSE);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXPrePowerState: Failed to submit power down command"));
@@ -263,8 +264,9 @@ PVRSRV_ERROR SGXPrePowerState (IMG_HANDLE hDevHandle,
if (PollForValueKM(&psDevInfo->psSGXHostCtl->ui32PowerStatus,
ui32CompleteStatus,
ui32CompleteStatus,
+ MAX_HW_TIME_US,
MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
+ IMG_FALSE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXPrePowerState: Wait for SGX ukernel power transition failed."));
PVR_DBG_BREAK;
@@ -371,7 +373,7 @@ PVRSRV_ERROR SGXPostPowerState (IMG_HANDLE hDevHandle,
SGXMKIF_COMMAND sCommand = {0};
sCommand.ui32Data[1] = PVRSRV_POWERCMD_RESUME;
- eError = SGXScheduleCCBCommand(psDevInfo, SGXMKIF_CMD_POWER, &sCommand, ISR_ID, 0);
+ eError = SGXScheduleCCBCommand(psDevInfo, SGXMKIF_CMD_POWER, &sCommand, ISR_ID, 0, IMG_FALSE);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXPostPowerState failed to schedule CCB command: %u", eError));
diff --git a/drivers/gpu/pvr/sgx/sgxreset.c b/drivers/gpu/pvr/sgx/sgxreset.c
index 57f6693..847ca24 100644
--- a/drivers/gpu/pvr/sgx/sgxreset.c
+++ b/drivers/gpu/pvr/sgx/sgxreset.c
@@ -199,8 +199,9 @@ static IMG_VOID SGXResetInvalDC(PVRSRV_SGXDEV_INFO *psDevInfo,
if (PollForValueKM((IMG_UINT32 *)((IMG_UINT8*)psDevInfo->pvRegsBaseKM + EUR_CR_BIF_MEM_REQ_STAT),
0,
EUR_CR_BIF_MEM_REQ_STAT_READS_MASK,
+ MAX_HW_TIME_US,
MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
+ IMG_FALSE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"Wait for DC invalidate failed."));
PVR_DBG_BREAK;
@@ -329,6 +330,13 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
ui32RegVal = EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_MASK;
+ #if defined(FIX_HW_BRN_31195)
+ ui32RegVal |= EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_MASK |
+ EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_MASK |
+ EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_MASK |
+ EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_MASK |
+ EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_MASK;
+ #endif
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
#endif
diff --git a/drivers/gpu/pvr/sgx/sgxtransfer.c b/drivers/gpu/pvr/sgx/sgxtransfer.c
index 317b73f..ab46ff7 100644
--- a/drivers/gpu/pvr/sgx/sgxtransfer.c
+++ b/drivers/gpu/pvr/sgx/sgxtransfer.c
@@ -131,7 +131,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
}
-
+
for (loop=0; loop<psKick->ui32NumSrcSync; loop++)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop];
@@ -146,7 +146,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
#if defined(PDUMP)
if ((PDumpIsCaptureFrameKM()
- || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
+ || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
&& (bPersistentProcess == IMG_FALSE) )
{
PDUMPCOMMENT("Shared part of transfer command\r\n");
@@ -194,7 +194,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal),
psKick->ui32PDumpFlags,
MAKEUNIQUETAG(psCCBMemInfo));
-
+
PDUMPCOMMENT("Hack dest surface read op in transfer cmd\r\n");
PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal,
psCCBMemInfo,
@@ -206,7 +206,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
}
}
-
+
if((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING)== 0UL)
{
for (loop=0; loop<(psKick->ui32NumSrcSync); loop++)
@@ -224,16 +224,16 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
psSyncInfo->psSyncData->ui32LastOpDumpVal++;
}
}
- }
+ }
#endif
sCommand.ui32Data[1] = psKick->sHWTransferContextDevVAddr.uiAddr;
-
- eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TRANSFER, &sCommand, KERNEL_ID, psKick->ui32PDumpFlags);
+
+ eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TRANSFER, &sCommand, KERNEL_ID, psKick->ui32PDumpFlags, IMG_FALSE);
if (eError == PVRSRV_ERROR_RETRY)
{
-
+
if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING) == 0UL)
{
if (psKick->ui32NumSrcSync > 0)
@@ -264,14 +264,14 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
#endif
}
-
+
if (psKick->hTASyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo;
psSyncInfo->psSyncData->ui32WriteOpsPending--;
}
-
+
if (psKick->h3DSyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo;
@@ -284,14 +284,14 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
PVR_DPF((PVR_DBG_ERROR, "SGXSubmitTransferKM: SGXScheduleCCBCommandKM failed."));
return eError;
}
-
+
#if defined(NO_HARDWARE)
if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_NOSYNCUPDATE) == 0)
{
IMG_UINT32 i;
-
+
for(i = 0; i < psKick->ui32NumSrcSync; i++)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[i];
@@ -326,7 +326,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
#if defined(SGX_FEATURE_2D_HARDWARE)
IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK *psKick)
-
+
{
PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psKick->hCCBMemInfo;
SGXMKIF_COMMAND sCommand = {0};
@@ -336,7 +336,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
IMG_UINT32 i;
#if defined(PDUMP)
IMG_BOOL bPersistentProcess = IMG_FALSE;
-
+
{
PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData();
if(psPerProc != IMG_NULL)
@@ -344,20 +344,20 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
bPersistentProcess = psPerProc->bPDumpPersistent;
}
}
-#endif
+#endif
if (!CCB_OFFSET_IS_VALID(SGXMKIF_2DCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset))
{
PVR_DPF((PVR_DBG_ERROR, "SGXSubmit2DKM: Invalid CCB offset"));
return PVRSRV_ERROR_INVALID_PARAMS;
}
-
-
+
+
ps2DCmd = CCB_DATA_FROM_OFFSET(SGXMKIF_2DCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset);
OSMemSet(ps2DCmd, 0, sizeof(*ps2DCmd));
-
+
if (psKick->hTASyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo;
@@ -365,11 +365,11 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
ps2DCmd->sTASyncData.ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++;
ps2DCmd->sTASyncData.ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending;
- ps2DCmd->sTASyncData.sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
- ps2DCmd->sTASyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
+ ps2DCmd->sTASyncData.sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
+ ps2DCmd->sTASyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
}
-
+
if (psKick->h3DSyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo;
@@ -381,7 +381,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
ps2DCmd->s3DSyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
}
-
+
ps2DCmd->ui32NumSrcSync = psKick->ui32NumSrcSync;
for (i = 0; i < psKick->ui32NumSrcSync; i++)
{
@@ -405,7 +405,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
ps2DCmd->sDstSyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
}
-
+
for (i = 0; i < psKick->ui32NumSrcSync; i++)
{
psSyncInfo = psKick->ahSrcSyncInfo[i];
@@ -423,7 +423,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
|| ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
&& (bPersistentProcess == IMG_FALSE) )
{
-
+
PDUMPCOMMENT("Shared part of 2D command\r\n");
PDUMPMEM(ps2DCmd,
psCCBMemInfo,
@@ -474,7 +474,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
MAKEUNIQUETAG(psCCBMemInfo));
}
-
+
for (i = 0; i < psKick->ui32NumSrcSync; i++)
{
psSyncInfo = psKick->ahSrcSyncInfo[i];
@@ -486,16 +486,16 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
psSyncInfo = psKick->hDstSyncInfo;
psSyncInfo->psSyncData->ui32LastOpDumpVal++;
}
- }
+ }
#endif
sCommand.ui32Data[1] = psKick->sHW2DContextDevVAddr.uiAddr;
-
- eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_2D, &sCommand, KERNEL_ID, psKick->ui32PDumpFlags);
+
+ eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_2D, &sCommand, KERNEL_ID, psKick->ui32PDumpFlags, IMG_FALSE);
if (eError == PVRSRV_ERROR_RETRY)
{
-
+
#if defined(PDUMP)
if (PDumpIsCaptureFrameKM())
diff --git a/drivers/gpu/pvr/sgx/sgxutils.c b/drivers/gpu/pvr/sgx/sgxutils.c
index 83144de..7f64088 100644
--- a/drivers/gpu/pvr/sgx/sgxutils.c
+++ b/drivers/gpu/pvr/sgx/sgxutils.c
@@ -142,7 +142,7 @@ static INLINE SGXMKIF_COMMAND * SGXAcquireKernelCCBSlot(PVRSRV_SGX_CCB_INFO *psC
return &psCCB->psCommands[*psCCB->pui32WriteOffset];
}
- OSWaitus(MAX_HW_TIME_US/WAIT_TRY_COUNT);
+ OSSleepms(1);
} END_LOOP_UNTIL_TIMEOUT();
@@ -153,12 +153,12 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
SGXMKIF_CMD_TYPE eCmdType,
SGXMKIF_COMMAND *psCommandData,
IMG_UINT32 ui32CallerID,
- IMG_UINT32 ui32PDumpFlags)
+ IMG_UINT32 ui32PDumpFlags,
+ IMG_BOOL bLastInScene)
{
PVRSRV_SGX_CCB_INFO *psKernelCCB;
PVRSRV_ERROR eError = PVRSRV_OK;
SGXMKIF_COMMAND *psSGXCommand;
- SYS_DATA *psSysData;
#if defined(PDUMP)
IMG_VOID *pvDumpCommand;
IMG_BOOL bPDumpIsSuspended = PDumpIsSuspended();
@@ -187,7 +187,8 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
SGXMKIF_CMD_PROCESS_QUEUES,
&sCacheCommand,
ui32CallerID,
- ui32PDumpFlags);
+ ui32PDumpFlags,
+ bLastInScene);
if (eError != PVRSRV_OK)
{
goto Exit;
@@ -198,8 +199,9 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
if(PollForValueKM(&psSGXHostCtl->ui32InvalStatus,
PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE,
PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE,
- 2 * MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
+ 2 * MAX_HW_TIME_US,
+ MAX_HW_TIME_US/WAIT_TRY_COUNT,
+ IMG_FALSE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXScheduleCCBCommand: Wait for uKernel to Invalidate BIF cache failed"));
PVR_DBG_BREAK;
@@ -224,7 +226,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
#endif
#if defined(PDUMP)
-
+
{
PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData();
if(psPerProc != IMG_NULL)
@@ -232,30 +234,30 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
bPersistentProcess = psPerProc->bPDumpPersistent;
}
}
-#endif
+#endif
psKernelCCB = psDevInfo->psKernelCCBInfo;
psSGXCommand = SGXAcquireKernelCCBSlot(psKernelCCB);
-
+
if(!psSGXCommand)
{
eError = PVRSRV_ERROR_TIMEOUT;
goto Exit;
}
-
+
psCommandData->ui32CacheControl = psDevInfo->ui32CacheControl;
#if defined(PDUMP)
-
+
psDevInfo->sPDContext.ui32CacheControl |= psDevInfo->ui32CacheControl;
#endif
-
+
psDevInfo->ui32CacheControl = 0;
-
+
*psSGXCommand = *psCommandData;
if (eCmdType >= SGXMKIF_CMD_MAX)
@@ -265,29 +267,34 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
goto Exit;
}
-
- SysAcquireData(&psSysData);
-
- if(psSysData->ePendingCacheOpType == PVRSRV_MISC_INFO_CPUCACHEOP_FLUSH)
+ if((eCmdType == SGXMKIF_CMD_TA) && bLastInScene)
{
- OSFlushCPUCacheKM();
- }
- else if(psSysData->ePendingCacheOpType == PVRSRV_MISC_INFO_CPUCACHEOP_CLEAN)
- {
- OSCleanCPUCacheKM();
- }
+ SYS_DATA *psSysData;
-
- psSysData->ePendingCacheOpType = PVRSRV_MISC_INFO_CPUCACHEOP_NONE;
+
+ SysAcquireData(&psSysData);
+
+ if(psSysData->ePendingCacheOpType == PVRSRV_MISC_INFO_CPUCACHEOP_FLUSH)
+ {
+ OSFlushCPUCacheKM();
+ }
+ else if(psSysData->ePendingCacheOpType == PVRSRV_MISC_INFO_CPUCACHEOP_CLEAN)
+ {
+ OSCleanCPUCacheKM();
+ }
+
+
+ psSysData->ePendingCacheOpType = PVRSRV_MISC_INFO_CPUCACHEOP_NONE;
+ }
PVR_ASSERT(eCmdType < SGXMKIF_CMD_MAX);
- psSGXCommand->ui32ServiceAddress = psDevInfo->aui32HostKickAddr[eCmdType];
+ psSGXCommand->ui32ServiceAddress = psDevInfo->aui32HostKickAddr[eCmdType];
#if defined(PDUMP)
if ((ui32CallerID != ISR_ID) && (bPDumpIsSuspended == IMG_FALSE) &&
(bPersistentProcess == IMG_FALSE) )
{
-
+
PDUMPCOMMENTWITHFLAGS(ui32PDumpFlags, "Poll for space in the Kernel CCB\r\n");
PDUMPMEMPOL(psKernelCCB->psCCBCtlMemInfo,
offsetof(PVRSRV_SGX_CCB_CTL, ui32ReadOffset),
@@ -307,7 +314,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
ui32PDumpFlags,
MAKEUNIQUETAG(psKernelCCB->psCCBMemInfo));
-
+
PDUMPMEM(&psDevInfo->sPDContext.ui32CacheControl,
psKernelCCB->psCCBMemInfo,
psKernelCCB->ui32CCBDumpWOff * sizeof(SGXMKIF_COMMAND) +
@@ -319,19 +326,20 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
if (PDumpIsCaptureFrameKM()
|| ((ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
{
-
+
psDevInfo->sPDContext.ui32CacheControl = 0;
}
}
#endif
#if defined(FIX_HW_BRN_26620) && defined(SGX_FEATURE_SYSTEM_CACHE) && !defined(SGX_BYPASS_SYSTEM_CACHE)
-
+
eError = PollForValueKM (psKernelCCB->pui32ReadOffset,
*psKernelCCB->pui32WriteOffset,
0xFF,
+ MAX_HW_TIME_US,
MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT);
+ IMG_FALSE);
if (eError != PVRSRV_OK)
{
eError = PVRSRV_ERROR_TIMEOUT;
@@ -339,7 +347,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
}
#endif
-
+
*psKernelCCB->pui32WriteOffset = (*psKernelCCB->pui32WriteOffset + 1) & 255;
@@ -405,7 +413,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
OSMemoryBarrier();
#if defined(NO_HARDWARE)
-
+
*psKernelCCB->pui32ReadOffset = (*psKernelCCB->pui32ReadOffset + 1) & 255;
#endif
@@ -418,7 +426,8 @@ PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode,
SGXMKIF_CMD_TYPE eCmdType,
SGXMKIF_COMMAND *psCommandData,
IMG_UINT32 ui32CallerID,
- IMG_UINT32 ui32PDumpFlags)
+ IMG_UINT32 ui32PDumpFlags,
+ IMG_BOOL bLastInScene)
{
PVRSRV_ERROR eError;
PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
@@ -465,7 +474,7 @@ PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode,
return eError;
}
- eError = SGXScheduleCCBCommand(psDevInfo, eCmdType, psCommandData, ui32CallerID, ui32PDumpFlags);
+ eError = SGXScheduleCCBCommand(psDevInfo, eCmdType, psCommandData, ui32CallerID, ui32PDumpFlags, bLastInScene);
PVRSRVPowerUnlock(ui32CallerID);
@@ -497,7 +506,7 @@ PVRSRV_ERROR SGXScheduleProcessQueuesKM(PVRSRV_DEVICE_NODE *psDeviceNode)
return PVRSRV_OK;
}
- eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_PROCESS_QUEUES, &sCommand, ISR_ID, 0);
+ eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_PROCESS_QUEUES, &sCommand, ISR_ID, 0, IMG_FALSE);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXScheduleProcessQueuesKM failed to schedule CCB command: %u", eError));
@@ -551,7 +560,7 @@ IMG_VOID SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode,
sCommand.ui32Data[0] = ui32CleanupType;
sCommand.ui32Data[1] = (psHWDataDevVAddr == IMG_NULL) ? 0 : psHWDataDevVAddr->uiAddr;
- eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_CLEANUP, &sCommand, KERNEL_ID, 0);
+ eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_CLEANUP, &sCommand, KERNEL_ID, 0, IMG_FALSE);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Failed to submit clean-up command"));
@@ -563,8 +572,9 @@ IMG_VOID SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode,
if(PollForValueKM(&psSGXHostCtl->ui32CleanupStatus,
PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
- 2 * MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
+ 10 * MAX_HW_TIME_US,
+ 1000,
+ IMG_TRUE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Wait for uKernel to clean up (%u) failed", ui32CleanupType));
PVR_DBG_BREAK;
@@ -943,7 +953,7 @@ PVRSRV_ERROR SGX2DQueryBlitsCompleteKM(PVRSRV_SGXDEV_INFO *psDevInfo,
LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US)
{
- OSWaitus(MAX_HW_TIME_US/WAIT_TRY_COUNT);
+ OSSleepms(1);
if(SGX2DQuerySyncOpsComplete(psSyncInfo, ui32ReadOpsPending, ui32WriteOpsPending))
{
@@ -952,7 +962,7 @@ PVRSRV_ERROR SGX2DQueryBlitsCompleteKM(PVRSRV_SGXDEV_INFO *psDevInfo,
return PVRSRV_OK;
}
- OSWaitus(MAX_HW_TIME_US/WAIT_TRY_COUNT);
+ OSSleepms(1);
} END_LOOP_UNTIL_TIMEOUT();
diff --git a/drivers/gpu/pvr/sgx/sgxutils.h b/drivers/gpu/pvr/sgx/sgxutils.h
index 7b6e473..ef03e4f 100644
--- a/drivers/gpu/pvr/sgx/sgxutils.h
+++ b/drivers/gpu/pvr/sgx/sgxutils.h
@@ -42,17 +42,19 @@ IMG_VOID SGXTestActivePowerEvent(PVRSRV_DEVICE_NODE *psDeviceNode,
IMG_UINT32 ui32CallerID);
IMG_IMPORT
-PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
+PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
SGXMKIF_CMD_TYPE eCommandType,
SGXMKIF_COMMAND *psCommandData,
IMG_UINT32 ui32CallerID,
- IMG_UINT32 ui32PDumpFlags);
+ IMG_UINT32 ui32PDumpFlags,
+ IMG_BOOL bLastInScene);
IMG_IMPORT
PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode,
SGXMKIF_CMD_TYPE eCommandType,
SGXMKIF_COMMAND *psCommandData,
IMG_UINT32 ui32CallerID,
- IMG_UINT32 ui32PDumpFlags);
+ IMG_UINT32 ui32PDumpFlags,
+ IMG_BOOL bLastInScene);
IMG_IMPORT
PVRSRV_ERROR SGXScheduleProcessQueuesKM(PVRSRV_DEVICE_NODE *psDeviceNode);
diff --git a/drivers/gpu/pvr/sgx543defs.h b/drivers/gpu/pvr/sgx543defs.h
new file mode 100644
index 0000000..ef8a06e
--- /dev/null
+++ b/drivers/gpu/pvr/sgx543defs.h
@@ -0,0 +1,1256 @@
+/**********************************************************************
+ *
+ * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful but, except
+ * as otherwise stated in writing, without any warranty; without even the
+ * implied warranty of merchantability or fitness for a particular purpose.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ *
+ * Contact Information:
+ * Imagination Technologies Ltd. <gpl-support@imgtec.com>
+ * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
+ *
+ ******************************************************************************/
+
+#ifndef _SGX543DEFS_KM_H_
+#define _SGX543DEFS_KM_H_
+
+#define EUR_CR_CLKGATECTL 0x0000
+#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U
+#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0
+#define EUR_CR_CLKGATECTL_ISP_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU
+#define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2
+#define EUR_CR_CLKGATECTL_ISP2_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U
+#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4
+#define EUR_CR_CLKGATECTL_TSP_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U
+#define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6
+#define EUR_CR_CLKGATECTL_TE_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U
+#define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8
+#define EUR_CR_CLKGATECTL_MTE_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U
+#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10
+#define EUR_CR_CLKGATECTL_DPM_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U
+#define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12
+#define EUR_CR_CLKGATECTL_VDM_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL_PDS_CLKG_MASK 0x0000C000U
+#define EUR_CR_CLKGATECTL_PDS_CLKG_SHIFT 14
+#define EUR_CR_CLKGATECTL_PDS_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_MASK 0x00030000U
+#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SHIFT 16
+#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U
+#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18
+#define EUR_CR_CLKGATECTL_TA_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U
+#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24
+#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SIGNED 0
+#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U
+#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28
+#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL2 0x0004
+#define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U
+#define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0
+#define EUR_CR_CLKGATECTL2_PBE_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_MASK 0x0000000CU
+#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SHIFT 2
+#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U
+#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4
+#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U
+#define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6
+#define EUR_CR_CLKGATECTL2_USE0_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U
+#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8
+#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U
+#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10
+#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U
+#define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14
+#define EUR_CR_CLKGATECTL2_USE1_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U
+#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16
+#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U
+#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18
+#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_MASK 0x00C00000U
+#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SHIFT 22
+#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_MASK 0x03000000U
+#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SHIFT 24
+#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SIGNED 0
+#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_MASK 0x0C000000U
+#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SHIFT 26
+#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SIGNED 0
+#define EUR_CR_CLKGATESTATUS 0x0008
+#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U
+#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0
+#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U
+#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1
+#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U
+#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2
+#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U
+#define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3
+#define EUR_CR_CLKGATESTATUS_TE_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U
+#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4
+#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U
+#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5
+#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U
+#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6
+#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_PDS_CLKS_MASK 0x00000080U
+#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SHIFT 7
+#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U
+#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8
+#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_MASK 0x00000200U
+#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SHIFT 9
+#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U
+#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10
+#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U
+#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11
+#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U
+#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12
+#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U
+#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13
+#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U
+#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15
+#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U
+#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16
+#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U
+#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17
+#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_MASK 0x00080000U
+#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19
+#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U
+#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20
+#define EUR_CR_CLKGATESTATUS_TA_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_MASK 0x00200000U
+#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SHIFT 21
+#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_MASK 0x00400000U
+#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SHIFT 22
+#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SIGNED 0
+#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_MASK 0x00800000U
+#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SHIFT 23
+#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SIGNED 0
+#define EUR_CR_CLKGATECTLOVR 0x000C
+#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U
+#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0
+#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SIGNED 0
+#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU
+#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2
+#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SIGNED 0
+#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U
+#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4
+#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SIGNED 0
+#define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U
+#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6
+#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SIGNED 0
+#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U
+#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8
+#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SIGNED 0
+#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U
+#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10
+#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SIGNED 0
+#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U
+#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12
+#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SIGNED 0
+#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_MASK 0x0000C000U
+#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SHIFT 14
+#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SIGNED 0
+#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_MASK 0x00030000U
+#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16
+#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SIGNED 0
+#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U
+#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18
+#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SIGNED 0
+#define EUR_CR_POWER 0x001C
+#define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U
+#define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0
+#define EUR_CR_POWER_PIPE_DISABLE_SIGNED 0
+#define EUR_CR_CORE_ID 0x0020
+#define EUR_CR_CORE_ID_CONFIG_MULTI_MASK 0x00000001U
+#define EUR_CR_CORE_ID_CONFIG_MULTI_SHIFT 0
+#define EUR_CR_CORE_ID_CONFIG_MULTI_SIGNED 0
+#define EUR_CR_CORE_ID_CONFIG_BASE_MASK 0x00000002U
+#define EUR_CR_CORE_ID_CONFIG_BASE_SHIFT 1
+#define EUR_CR_CORE_ID_CONFIG_BASE_SIGNED 0
+#define EUR_CR_CORE_ID_CONFIG_MASK 0x000000FCU
+#define EUR_CR_CORE_ID_CONFIG_SHIFT 2
+#define EUR_CR_CORE_ID_CONFIG_SIGNED 0
+#define EUR_CR_CORE_ID_CONFIG_CORES_MASK 0x00000F00U
+#define EUR_CR_CORE_ID_CONFIG_CORES_SHIFT 8
+#define EUR_CR_CORE_ID_CONFIG_CORES_SIGNED 0
+#define EUR_CR_CORE_ID_CONFIG_SLC_MASK 0x0000F000U
+#define EUR_CR_CORE_ID_CONFIG_SLC_SHIFT 12
+#define EUR_CR_CORE_ID_CONFIG_SLC_SIGNED 0
+#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U
+#define EUR_CR_CORE_ID_ID_SHIFT 16
+#define EUR_CR_CORE_ID_ID_SIGNED 0
+#define EUR_CR_CORE_REVISION 0x0024
+#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU
+#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0
+#define EUR_CR_CORE_REVISION_MAINTENANCE_SIGNED 0
+#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U
+#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8
+#define EUR_CR_CORE_REVISION_MINOR_SIGNED 0
+#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U
+#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16
+#define EUR_CR_CORE_REVISION_MAJOR_SIGNED 0
+#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U
+#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24
+#define EUR_CR_CORE_REVISION_DESIGNER_SIGNED 0
+#define EUR_CR_DESIGNER_REV_FIELD1 0x0028
+#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU
+#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0
+#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SIGNED 0
+#define EUR_CR_DESIGNER_REV_FIELD2 0x002C
+#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU
+#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0
+#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SIGNED 0
+#define EUR_CR_SOFT_RESET 0x0080
+#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U
+#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0
+#define EUR_CR_SOFT_RESET_BIF_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_VDM_RESET_MASK 0x00000002U
+#define EUR_CR_SOFT_RESET_VDM_RESET_SHIFT 1
+#define EUR_CR_SOFT_RESET_VDM_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U
+#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2
+#define EUR_CR_SOFT_RESET_DPM_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_TE_RESET_MASK 0x00000008U
+#define EUR_CR_SOFT_RESET_TE_RESET_SHIFT 3
+#define EUR_CR_SOFT_RESET_TE_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_MTE_RESET_MASK 0x00000010U
+#define EUR_CR_SOFT_RESET_MTE_RESET_SHIFT 4
+#define EUR_CR_SOFT_RESET_MTE_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U
+#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5
+#define EUR_CR_SOFT_RESET_ISP_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_ISP2_RESET_MASK 0x00000040U
+#define EUR_CR_SOFT_RESET_ISP2_RESET_SHIFT 6
+#define EUR_CR_SOFT_RESET_ISP2_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000080U
+#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 7
+#define EUR_CR_SOFT_RESET_TSP_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_PDS_RESET_MASK 0x00000100U
+#define EUR_CR_SOFT_RESET_PDS_RESET_SHIFT 8
+#define EUR_CR_SOFT_RESET_PDS_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_PBE_RESET_MASK 0x00000200U
+#define EUR_CR_SOFT_RESET_PBE_RESET_SHIFT 9
+#define EUR_CR_SOFT_RESET_PBE_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_TCU_L2_RESET_MASK 0x00000400U
+#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SHIFT 10
+#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK 0x00000800U
+#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SHIFT 11
+#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_ITR_RESET_MASK 0x00002000U
+#define EUR_CR_SOFT_RESET_ITR_RESET_SHIFT 13
+#define EUR_CR_SOFT_RESET_ITR_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_TEX_RESET_MASK 0x00004000U
+#define EUR_CR_SOFT_RESET_TEX_RESET_SHIFT 14
+#define EUR_CR_SOFT_RESET_TEX_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00008000U
+#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 15
+#define EUR_CR_SOFT_RESET_USE_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK 0x00010000U
+#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16
+#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U
+#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17
+#define EUR_CR_SOFT_RESET_TA_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_DCU_L2_RESET_MASK 0x00040000U
+#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SHIFT 18
+#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SIGNED 0
+#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK 0x00080000U
+#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SHIFT 19
+#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE2 0x0110
+#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U
+#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11
+#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U
+#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SHIFT 10
+#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_MASK 0x00000200U
+#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SHIFT 9
+#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U
+#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SHIFT 8
+#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_MASK 0x00000080U
+#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SHIFT 7
+#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_MASK 0x00000040U
+#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SHIFT 6
+#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U
+#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5
+#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U
+#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4
+#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U
+#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3
+#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U
+#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2
+#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U
+#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1
+#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U
+#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0
+#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR2 0x0114
+#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U
+#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11
+#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U
+#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SHIFT 10
+#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_MASK 0x00000200U
+#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SHIFT 9
+#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U
+#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SHIFT 8
+#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_MASK 0x00000080U
+#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SHIFT 7
+#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_MASK 0x00000040U
+#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SHIFT 6
+#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U
+#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5
+#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U
+#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4
+#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U
+#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3
+#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U
+#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2
+#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U
+#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1
+#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U
+#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0
+#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SIGNED 0
+#define EUR_CR_EVENT_STATUS2 0x0118
+#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U
+#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11
+#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0
+#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U
+#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SHIFT 10
+#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SIGNED 0
+#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_MASK 0x00000200U
+#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SHIFT 9
+#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SIGNED 0
+#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U
+#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SHIFT 8
+#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SIGNED 0
+#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_MASK 0x00000080U
+#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SHIFT 7
+#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SIGNED 0
+#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_MASK 0x00000040U
+#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SHIFT 6
+#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SIGNED 0
+#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U
+#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5
+#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0
+#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U
+#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4
+#define EUR_CR_EVENT_STATUS2_TRIG_TA_SIGNED 0
+#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U
+#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3
+#define EUR_CR_EVENT_STATUS2_TRIG_3D_SIGNED 0
+#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U
+#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2
+#define EUR_CR_EVENT_STATUS2_TRIG_DL_SIGNED 0
+#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U
+#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1
+#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SIGNED 0
+#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U
+#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0
+#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SIGNED 0
+#define EUR_CR_EVENT_STATUS 0x012C
+#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U
+#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31
+#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SIGNED 0
+#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U
+#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29
+#define EUR_CR_EVENT_STATUS_TIMER_SIGNED 0
+#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U
+#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28
+#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SIGNED 0
+#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_MASK 0x04000000U
+#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SHIFT 26
+#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
+#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
+#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U
+#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24
+#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SIGNED 0
+#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U
+#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23
+#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U
+#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22
+#define EUR_CR_EVENT_STATUS_DPM_INITEND_SIGNED 0
+#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U
+#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21
+#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SIGNED 0
+#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U
+#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20
+#define EUR_CR_EVENT_STATUS_OTPM_INV_SIGNED 0
+#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U
+#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19
+#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SIGNED 0
+#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U
+#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18
+#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SIGNED 0
+#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U
+#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15
+#define EUR_CR_EVENT_STATUS_BREAKPOINT_SIGNED 0
+#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U
+#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14
+#define EUR_CR_EVENT_STATUS_SW_EVENT_SIGNED 0
+#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U
+#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13
+#define EUR_CR_EVENT_STATUS_TA_FINISHED_SIGNED 0
+#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U
+#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12
+#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SIGNED 0
+#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U
+#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11
+#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SIGNED 0
+#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U
+#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10
+#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U
+#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9
+#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U
+#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8
+#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U
+#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7
+#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U
+#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6
+#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U
+#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5
+#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U
+#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4
+#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
+#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3
+#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
+#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
+#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
+#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1
+#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SIGNED 0
+#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U
+#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0
+#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE 0x0130
+#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U
+#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31
+#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U
+#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29
+#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U
+#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28
+#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_MASK 0x04000000U
+#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SHIFT 26
+#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U
+#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23
+#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U
+#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21
+#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U
+#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20
+#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U
+#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19
+#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U
+#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18
+#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U
+#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15
+#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U
+#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14
+#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U
+#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13
+#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U
+#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12
+#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U
+#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11
+#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U
+#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10
+#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SIGNED 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0
+#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR 0x0134
+#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U
+#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31
+#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U
+#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29
+#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U
+#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28
+#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_MASK 0x04000000U
+#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SHIFT 26
+#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U
+#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23
+#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U
+#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21
+#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U
+#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20
+#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U
+#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19
+#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U
+#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18
+#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U
+#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15
+#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U
+#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14
+#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U
+#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13
+#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U
+#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12
+#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U
+#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11
+#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U
+#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10
+#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SIGNED 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0
+#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SIGNED 0
+#define EUR_CR_TIMER 0x0144
+#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU
+#define EUR_CR_TIMER_VALUE_SHIFT 0
+#define EUR_CR_TIMER_VALUE_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_0 0x0A0C
+#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_00_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_1 0x0A10
+#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_01_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_2 0x0A14
+#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_02_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_3 0x0A18
+#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_03_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_4 0x0A1C
+#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_04_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_5 0x0A20
+#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_05_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_6 0x0A24
+#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_06_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_7 0x0A28
+#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_07_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_8 0x0A2C
+#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_08_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_9 0x0A30
+#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_09_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_10 0x0A34
+#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_10_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_11 0x0A38
+#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_11_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_12 0x0A3C
+#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_12_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_13 0x0A40
+#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_13_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_14 0x0A44
+#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_14_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_15 0x0A48
+#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_15_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0
+#define EUR_CR_EVENT_KICK1 0x0AB0
+#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU
+#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0
+#define EUR_CR_EVENT_KICK1_NOW_SIGNED 0
+#define EUR_CR_EVENT_KICK2 0x0AC0
+#define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U
+#define EUR_CR_EVENT_KICK2_NOW_SHIFT 0
+#define EUR_CR_EVENT_KICK2_NOW_SIGNED 0
+#define EUR_CR_EVENT_KICKER 0x0AC4
+#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4
+#define EUR_CR_EVENT_KICKER_ADDRESS_SIGNED 0
+#define EUR_CR_EVENT_KICK 0x0AC8
+#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U
+#define EUR_CR_EVENT_KICK_NOW_SHIFT 0
+#define EUR_CR_EVENT_KICK_NOW_SIGNED 0
+#define EUR_CR_EVENT_TIMER 0x0ACC
+#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U
+#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24
+#define EUR_CR_EVENT_TIMER_ENABLE_SIGNED 0
+#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU
+#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0
+#define EUR_CR_EVENT_TIMER_VALUE_SIGNED 0
+#define EUR_CR_PDS_INV0 0x0AD0
+#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U
+#define EUR_CR_PDS_INV0_DSC_SHIFT 0
+#define EUR_CR_PDS_INV0_DSC_SIGNED 0
+#define EUR_CR_PDS_INV1 0x0AD4
+#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U
+#define EUR_CR_PDS_INV1_DSC_SHIFT 0
+#define EUR_CR_PDS_INV1_DSC_SIGNED 0
+#define EUR_CR_EVENT_KICK3 0x0AD8
+#define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U
+#define EUR_CR_EVENT_KICK3_NOW_SHIFT 0
+#define EUR_CR_EVENT_KICK3_NOW_SIGNED 0
+#define EUR_CR_PDS_INV3 0x0ADC
+#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U
+#define EUR_CR_PDS_INV3_DSC_SHIFT 0
+#define EUR_CR_PDS_INV3_DSC_SIGNED 0
+#define EUR_CR_PDS_INV_CSC 0x0AE0
+#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U
+#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0
+#define EUR_CR_PDS_INV_CSC_KICK_SIGNED 0
+#define EUR_CR_BIF_CTRL 0x0C00
+#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U
+#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0
+#define EUR_CR_BIF_CTRL_NOREORDER_SIGNED 0
+#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U
+#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1
+#define EUR_CR_BIF_CTRL_PAUSE_SIGNED 0
+#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U
+#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4
+#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SIGNED 0
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SIGNED 0
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_MASK 0x00000400U
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SHIFT 10
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SIGNED 0
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SIGNED 0
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SIGNED 0
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SIGNED 0
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SIGNED 0
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_MASK 0x00010000U
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SHIFT 16
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SIGNED 0
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_MASK 0x00020000U
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SHIFT 17
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SIGNED 0
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_MASK 0x00040000U
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SHIFT 18
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SIGNED 0
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19
+#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0
+#define EUR_CR_BIF_INT_STAT 0x0C04
+#define EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK 0x00003FFFU
+#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SHIFT 0
+#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SIGNED 0
+#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK 0x00070000U
+#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SHIFT 16
+#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SIGNED 0
+#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00080000U
+#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 19
+#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SIGNED 0
+#define EUR_CR_BIF_FAULT 0x0C08
+#define EUR_CR_BIF_FAULT_CID_MASK 0x0000000FU
+#define EUR_CR_BIF_FAULT_CID_SHIFT 0
+#define EUR_CR_BIF_FAULT_CID_SIGNED 0
+#define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U
+#define EUR_CR_BIF_FAULT_SB_SHIFT 4
+#define EUR_CR_BIF_FAULT_SB_SIGNED 0
+#define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U
+#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12
+#define EUR_CR_BIF_FAULT_ADDR_SIGNED 0
+#define EUR_CR_BIF_TILE0 0x0C0C
+#define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU
+#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0
+#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U
+#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12
+#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U
+#define EUR_CR_BIF_TILE0_CFG_SHIFT 24
+#define EUR_CR_BIF_TILE0_CFG_SIGNED 0
+#define EUR_CR_BIF_TILE1 0x0C10
+#define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU
+#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0
+#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U
+#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12
+#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U
+#define EUR_CR_BIF_TILE1_CFG_SHIFT 24
+#define EUR_CR_BIF_TILE1_CFG_SIGNED 0
+#define EUR_CR_BIF_TILE2 0x0C14
+#define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU
+#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0
+#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U
+#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12
+#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U
+#define EUR_CR_BIF_TILE2_CFG_SHIFT 24
+#define EUR_CR_BIF_TILE2_CFG_SIGNED 0
+#define EUR_CR_BIF_TILE3 0x0C18
+#define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU
+#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0
+#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U
+#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12
+#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U
+#define EUR_CR_BIF_TILE3_CFG_SHIFT 24
+#define EUR_CR_BIF_TILE3_CFG_SIGNED 0
+#define EUR_CR_BIF_TILE4 0x0C1C
+#define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU
+#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0
+#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U
+#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12
+#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U
+#define EUR_CR_BIF_TILE4_CFG_SHIFT 24
+#define EUR_CR_BIF_TILE4_CFG_SIGNED 0
+#define EUR_CR_BIF_TILE5 0x0C20
+#define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU
+#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0
+#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U
+#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12
+#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U
+#define EUR_CR_BIF_TILE5_CFG_SHIFT 24
+#define EUR_CR_BIF_TILE5_CFG_SIGNED 0
+#define EUR_CR_BIF_TILE6 0x0C24
+#define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU
+#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0
+#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U
+#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12
+#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U
+#define EUR_CR_BIF_TILE6_CFG_SHIFT 24
+#define EUR_CR_BIF_TILE6_CFG_SIGNED 0
+#define EUR_CR_BIF_TILE7 0x0C28
+#define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU
+#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0
+#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U
+#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12
+#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U
+#define EUR_CR_BIF_TILE7_CFG_SHIFT 24
+#define EUR_CR_BIF_TILE7_CFG_SIGNED 0
+#define EUR_CR_BIF_TILE8 0x0C2C
+#define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU
+#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0
+#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U
+#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12
+#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U
+#define EUR_CR_BIF_TILE8_CFG_SHIFT 24
+#define EUR_CR_BIF_TILE8_CFG_SIGNED 0
+#define EUR_CR_BIF_TILE9 0x0C30
+#define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU
+#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0
+#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U
+#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12
+#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SIGNED 0
+#define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U
+#define EUR_CR_BIF_TILE9_CFG_SHIFT 24
+#define EUR_CR_BIF_TILE9_CFG_SIGNED 0
+#define EUR_CR_BIF_CTRL_INVAL 0x0C34
+#define EUR_CR_BIF_CTRL_INVAL_PTE_MASK 0x00000004U
+#define EUR_CR_BIF_CTRL_INVAL_PTE_SHIFT 2
+#define EUR_CR_BIF_CTRL_INVAL_PTE_SIGNED 0
+#define EUR_CR_BIF_CTRL_INVAL_ALL_MASK 0x00000008U
+#define EUR_CR_BIF_CTRL_INVAL_ALL_SHIFT 3
+#define EUR_CR_BIF_CTRL_INVAL_ALL_SIGNED 0
+#define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38
+#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U
+#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12
+#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SIGNED 0
+#define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C
+#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U
+#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12
+#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SIGNED 0
+#define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40
+#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U
+#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12
+#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SIGNED 0
+#define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44
+#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U
+#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12
+#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SIGNED 0
+#define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48
+#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U
+#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12
+#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SIGNED 0
+#define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C
+#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U
+#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12
+#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SIGNED 0
+#define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50
+#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U
+#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12
+#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SIGNED 0
+#define EUR_CR_BIF_BANK_SET 0x0C74
+#define EUR_CR_BIF_BANK_SET_SELECT_2D_MASK 0x00000001U
+#define EUR_CR_BIF_BANK_SET_SELECT_2D_SHIFT 0
+#define EUR_CR_BIF_BANK_SET_SELECT_2D_SIGNED 0
+#define EUR_CR_BIF_BANK_SET_SELECT_3D_MASK 0x0000000CU
+#define EUR_CR_BIF_BANK_SET_SELECT_3D_SHIFT 2
+#define EUR_CR_BIF_BANK_SET_SELECT_3D_SIGNED 0
+#define EUR_CR_BIF_BANK_SET_SELECT_HOST_MASK 0x00000010U
+#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SHIFT 4
+#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SIGNED 0
+#define EUR_CR_BIF_BANK_SET_SELECT_TA_MASK 0x000000C0U
+#define EUR_CR_BIF_BANK_SET_SELECT_TA_SHIFT 6
+#define EUR_CR_BIF_BANK_SET_SELECT_TA_SIGNED 0
+#define EUR_CR_BIF_BANK_SET_SELECT_EDM_MASK 0x00000100U
+#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SHIFT 8
+#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SIGNED 0
+#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_MASK 0x00000200U
+#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SHIFT 9
+#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SIGNED 0
+#define EUR_CR_BIF_BANK0 0x0C78
+#define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU
+#define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0
+#define EUR_CR_BIF_BANK0_INDEX_EDM_SIGNED 0
+#define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U
+#define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4
+#define EUR_CR_BIF_BANK0_INDEX_TA_SIGNED 0
+#define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U
+#define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12
+#define EUR_CR_BIF_BANK0_INDEX_3D_SIGNED 0
+#define EUR_CR_BIF_BANK0_INDEX_PTLA_MASK 0x000F0000U
+#define EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT 16
+#define EUR_CR_BIF_BANK0_INDEX_PTLA_SIGNED 0
+#define EUR_CR_BIF_BANK1 0x0C7C
+#define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU
+#define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0
+#define EUR_CR_BIF_BANK1_INDEX_EDM_SIGNED 0
+#define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U
+#define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4
+#define EUR_CR_BIF_BANK1_INDEX_TA_SIGNED 0
+#define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U
+#define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12
+#define EUR_CR_BIF_BANK1_INDEX_3D_SIGNED 0
+#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84
+#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U
+#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12
+#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SIGNED 0
+#define EUR_CR_BIF_TA_REQ_BASE 0x0C90
+#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U
+#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20
+#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SIGNED 0
+#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8
+#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU
+#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0
+#define EUR_CR_BIF_MEM_REQ_STAT_READS_SIGNED 0
+#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC
+#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U
+#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20
+#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SIGNED 0
+#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0
+#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U
+#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20
+#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SIGNED 0
+#define EUR_CR_BIF_BANK_STATUS 0x0CB4
+#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U
+#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0
+#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SIGNED 0
+#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U
+#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1
+#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0
+#define EUR_CR_2D_BLIT_STATUS 0x0E04
+#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU
+#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0
+#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SIGNED 0
+#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U
+#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24
+#define EUR_CR_2D_BLIT_STATUS_BUSY_SIGNED 0
+#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10
+#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U
+#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0
+#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SIGNED 0
+#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU
+#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1
+#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SIGNED 0
+#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U
+#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4
+#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SIGNED 0
+#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U
+#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12
+#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SIGNED 0
+#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14
+#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU
+#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0
+#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SIGNED 0
+#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U
+#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12
+#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SIGNED 0
+#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U
+#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24
+#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SIGNED 0
+#define EUR_CR_BREAKPOINT0_START 0x0F44
+#define EUR_CR_BREAKPOINT0_START_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_BREAKPOINT0_START_ADDRESS_SHIFT 4
+#define EUR_CR_BREAKPOINT0_START_ADDRESS_SIGNED 0
+#define EUR_CR_BREAKPOINT0_END 0x0F48
+#define EUR_CR_BREAKPOINT0_END_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_BREAKPOINT0_END_ADDRESS_SHIFT 4
+#define EUR_CR_BREAKPOINT0_END_ADDRESS_SIGNED 0
+#define EUR_CR_BREAKPOINT0 0x0F4C
+#define EUR_CR_BREAKPOINT0_MASK_DM_MASK 0x00000038U
+#define EUR_CR_BREAKPOINT0_MASK_DM_SHIFT 3
+#define EUR_CR_BREAKPOINT0_MASK_DM_SIGNED 0
+#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_MASK 0x00000004U
+#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SHIFT 2
+#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SIGNED 0
+#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_MASK 0x00000002U
+#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SHIFT 1
+#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SIGNED 0
+#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_MASK 0x00000001U
+#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SHIFT 0
+#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SIGNED 0
+#define EUR_CR_BREAKPOINT1_START 0x0F50
+#define EUR_CR_BREAKPOINT1_START_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_BREAKPOINT1_START_ADDRESS_SHIFT 4
+#define EUR_CR_BREAKPOINT1_START_ADDRESS_SIGNED 0
+#define EUR_CR_BREAKPOINT1_END 0x0F54
+#define EUR_CR_BREAKPOINT1_END_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_BREAKPOINT1_END_ADDRESS_SHIFT 4
+#define EUR_CR_BREAKPOINT1_END_ADDRESS_SIGNED 0
+#define EUR_CR_BREAKPOINT1 0x0F58
+#define EUR_CR_BREAKPOINT1_MASK_DM_MASK 0x00000038U
+#define EUR_CR_BREAKPOINT1_MASK_DM_SHIFT 3
+#define EUR_CR_BREAKPOINT1_MASK_DM_SIGNED 0
+#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_MASK 0x00000004U
+#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SHIFT 2
+#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SIGNED 0
+#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_MASK 0x00000002U
+#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SHIFT 1
+#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SIGNED 0
+#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_MASK 0x00000001U
+#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SHIFT 0
+#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SIGNED 0
+#define EUR_CR_BREAKPOINT2_START 0x0F5C
+#define EUR_CR_BREAKPOINT2_START_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_BREAKPOINT2_START_ADDRESS_SHIFT 4
+#define EUR_CR_BREAKPOINT2_START_ADDRESS_SIGNED 0
+#define EUR_CR_BREAKPOINT2_END 0x0F60
+#define EUR_CR_BREAKPOINT2_END_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_BREAKPOINT2_END_ADDRESS_SHIFT 4
+#define EUR_CR_BREAKPOINT2_END_ADDRESS_SIGNED 0
+#define EUR_CR_BREAKPOINT2 0x0F64
+#define EUR_CR_BREAKPOINT2_MASK_DM_MASK 0x00000038U
+#define EUR_CR_BREAKPOINT2_MASK_DM_SHIFT 3
+#define EUR_CR_BREAKPOINT2_MASK_DM_SIGNED 0
+#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_MASK 0x00000004U
+#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SHIFT 2
+#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SIGNED 0
+#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_MASK 0x00000002U
+#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SHIFT 1
+#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SIGNED 0
+#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_MASK 0x00000001U
+#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SHIFT 0
+#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SIGNED 0
+#define EUR_CR_BREAKPOINT3_START 0x0F68
+#define EUR_CR_BREAKPOINT3_START_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_BREAKPOINT3_START_ADDRESS_SHIFT 4
+#define EUR_CR_BREAKPOINT3_START_ADDRESS_SIGNED 0
+#define EUR_CR_BREAKPOINT3_END 0x0F6C
+#define EUR_CR_BREAKPOINT3_END_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_BREAKPOINT3_END_ADDRESS_SHIFT 4
+#define EUR_CR_BREAKPOINT3_END_ADDRESS_SIGNED 0
+#define EUR_CR_BREAKPOINT3 0x0F70
+#define EUR_CR_BREAKPOINT3_MASK_DM_MASK 0x00000038U
+#define EUR_CR_BREAKPOINT3_MASK_DM_SHIFT 3
+#define EUR_CR_BREAKPOINT3_MASK_DM_SIGNED 0
+#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_MASK 0x00000004U
+#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SHIFT 2
+#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SIGNED 0
+#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_MASK 0x00000002U
+#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SHIFT 1
+#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SIGNED 0
+#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_MASK 0x00000001U
+#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SHIFT 0
+#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SIGNED 0
+#define EUR_CR_BREAKPOINT_READ 0x0F74
+#define EUR_CR_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_BREAKPOINT_READ_ADDRESS_SHIFT 4
+#define EUR_CR_BREAKPOINT_READ_ADDRESS_SIGNED 0
+#define EUR_CR_BREAKPOINT_TRAP 0x0F78
+#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U
+#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_SHIFT 1
+#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_SIGNED 0
+#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U
+#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0
+#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0
+#define EUR_CR_BREAKPOINT 0x0F7C
+#define EUR_CR_BREAKPOINT_UNTRAPPED_MASK 0x00000008U
+#define EUR_CR_BREAKPOINT_UNTRAPPED_SHIFT 3
+#define EUR_CR_BREAKPOINT_UNTRAPPED_SIGNED 0
+#define EUR_CR_BREAKPOINT_TRAPPED_MASK 0x00000004U
+#define EUR_CR_BREAKPOINT_TRAPPED_SHIFT 2
+#define EUR_CR_BREAKPOINT_TRAPPED_SIGNED 0
+#define EUR_CR_BREAKPOINT_TRAP_INFO0 0x0F80
+#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4
+#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0
+#define EUR_CR_BREAKPOINT_TRAP_INFO1 0x0F84
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0
+#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0
+#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X)))
+#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x03FFFFFFU
+#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0
+#define EUR_CR_USE_CODE_BASE_ADDR_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_DM_MASK 0x0C000000U
+#define EUR_CR_USE_CODE_BASE_DM_SHIFT 26
+#define EUR_CR_USE_CODE_BASE_DM_SIGNED 0
+#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16
+#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16
+
+#endif
+
diff --git a/drivers/gpu/pvr/sgxinfo.h b/drivers/gpu/pvr/sgxinfo.h
index eaef12f..50f1113 100644
--- a/drivers/gpu/pvr/sgxinfo.h
+++ b/drivers/gpu/pvr/sgxinfo.h
@@ -175,6 +175,7 @@ typedef struct _SGX_CCB_KICK_
#if (defined(NO_HARDWARE) || defined(PDUMP))
IMG_BOOL bTerminateOrAbort;
#endif
+ IMG_BOOL bLastInScene;
IMG_UINT32 ui32CCBOffset;
diff --git a/drivers/gpu/pvr/sgxmpdefs.h b/drivers/gpu/pvr/sgxmpdefs.h
new file mode 100644
index 0000000..b1b67bf
--- /dev/null
+++ b/drivers/gpu/pvr/sgxmpdefs.h
@@ -0,0 +1,306 @@
+/**********************************************************************
+ *
+ * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful but, except
+ * as otherwise stated in writing, without any warranty; without even the
+ * implied warranty of merchantability or fitness for a particular purpose.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ *
+ * Contact Information:
+ * Imagination Technologies Ltd. <gpl-support@imgtec.com>
+ * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
+ *
+ ******************************************************************************/
+
+#ifndef _SGXMPDEFS_KM_H_
+#define _SGXMPDEFS_KM_H_
+
+#define EUR_CR_MASTER_BIF_CTRL 0x4C00
+#define EUR_CR_MASTER_BIF_CTRL_NOREORDER_MASK 0x00000001U
+#define EUR_CR_MASTER_BIF_CTRL_NOREORDER_SHIFT 0
+#define EUR_CR_MASTER_BIF_CTRL_NOREORDER_SIGNED 0
+#define EUR_CR_MASTER_BIF_CTRL_PAUSE_MASK 0x00000002U
+#define EUR_CR_MASTER_BIF_CTRL_PAUSE_SHIFT 1
+#define EUR_CR_MASTER_BIF_CTRL_PAUSE_SIGNED 0
+#define EUR_CR_MASTER_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U
+#define EUR_CR_MASTER_BIF_CTRL_CLEAR_FAULT_SHIFT 4
+#define EUR_CR_MASTER_BIF_CTRL_CLEAR_FAULT_SIGNED 0
+#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_PTLA_MASK 0x00010000U
+#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_PTLA_SHIFT 16
+#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_PTLA_SIGNED 0
+#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_VDM_MASK 0x00020000U
+#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SHIFT 17
+#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SIGNED 0
+#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_IPF_MASK 0x00040000U
+#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SHIFT 18
+#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SIGNED 0
+#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U
+#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19
+#define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0
+#define EUR_CR_MASTER_BIF_CTRL_INVAL 0x4C34
+#define EUR_CR_MASTER_BIF_CTRL_INVAL_PTE_MASK 0x00000004U
+#define EUR_CR_MASTER_BIF_CTRL_INVAL_PTE_SHIFT 2
+#define EUR_CR_MASTER_BIF_CTRL_INVAL_PTE_SIGNED 0
+#define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_MASK 0x00000008U
+#define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_SHIFT 3
+#define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL 0x4D00
+#define EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_MASK 0x00800000U
+#define EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_SHIFT 23
+#define EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_DISABLE_BURST_EXP_MASK 0x00400000U
+#define EUR_CR_MASTER_SLC_CTRL_DISABLE_BURST_EXP_SHIFT 22
+#define EUR_CR_MASTER_SLC_CTRL_DISABLE_BURST_EXP_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ3_MASK 0x00200000U
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ3_SHIFT 21
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ3_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ2_MASK 0x00100000U
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ2_SHIFT 20
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ2_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ1_MASK 0x00080000U
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ1_SHIFT 19
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ1_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_MASK 0x00040000U
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_SHIFT 18
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_DM_REF_SET_ALL_MASK 0x00010000U
+#define EUR_CR_MASTER_SLC_CTRL_DM_REF_SET_ALL_SHIFT 16
+#define EUR_CR_MASTER_SLC_CTRL_DM_REF_SET_ALL_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_MASK 0x0000F000U
+#define EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SHIFT 12
+#define EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_MASK 0x00000E00U
+#define EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SHIFT 9
+#define EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_PAUSE_MASK 0x00000100U
+#define EUR_CR_MASTER_SLC_CTRL_PAUSE_SHIFT 8
+#define EUR_CR_MASTER_SLC_CTRL_PAUSE_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS 0x4D04
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_N_MASK 0x08000000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_N_SHIFT 27
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_N_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_MASK 0x04000000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_SHIFT 26
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE4_MASK 0x02000000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE4_SHIFT 25
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE4_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE3_MASK 0x01000000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE3_SHIFT 24
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE3_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE2_MASK 0x00800000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE2_SHIFT 23
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE2_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE1_MASK 0x00400000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE1_SHIFT 22
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE1_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE0_MASK 0x00200000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE0_SHIFT 21
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_CORE0_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PTLA_MASK 0x00100000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PTLA_SHIFT 20
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PTLA_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_ISP2_RCIF_MASK 0x00080000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_ISP2_RCIF_SHIFT 19
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_ISP2_RCIF_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_ZLS_MASK 0x00040000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_ZLS_SHIFT 18
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_ZLS_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PBE_MASK 0x00020000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PBE_SHIFT 17
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PBE_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_VDM_MASK 0x00010000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_VDM_SHIFT 16
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_VDM_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_IPF_MASK 0x00008000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_IPF_SHIFT 15
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_IPF_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PDS_MASK 0x00004000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PDS_SHIFT 14
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_PDS_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USEC_MASK 0x00002000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USEC_SHIFT 13
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USEC_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_MASK 0x00001000U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_SHIFT 12
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_MASK 0x00000800U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_SHIFT 11
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_MASK 0x00000400U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_SHIFT 10
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_MASK 0x00000200U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_SHIFT 9
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_IPF_OBJ_MASK 0x00000100U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_IPF_OBJ_SHIFT 8
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_IPF_OBJ_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TPF_MASK 0x00000080U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TPF_SHIFT 7
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TPF_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_MASK 0x00000040U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_SHIFT 6
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_CACHE_MASK 0x00000020U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_CACHE_SHIFT 5
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_CACHE_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_MMU_MASK 0x00000010U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_MMU_SHIFT 4
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_MMU_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_EVENT_MASK 0x00000008U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_EVENT_SHIFT 3
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_EVENT_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_PIXEL_MASK 0x00000004U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_PIXEL_SHIFT 2
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_PIXEL_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_VERTEX_MASK 0x00000002U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_VERTEX_SHIFT 1
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_DM_VERTEX_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_ALL_MASK 0x00000001U
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_ALL_SHIFT 0
+#define EUR_CR_MASTER_SLC_CTRL_BYPASS_ALL_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL 0x4D08
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_ADDR_MASK 0xFFFFFFFFU
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_ADDR_SHIFT 0
+#define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_ADDR_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_INVAL 0x4D28
+#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_EVENT_MASK 0x00000008U
+#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_EVENT_SHIFT 3
+#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_EVENT_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_PIXEL_MASK 0x00000004U
+#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_PIXEL_SHIFT 2
+#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_PIXEL_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_VERTEX_MASK 0x00000002U
+#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_VERTEX_SHIFT 1
+#define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_VERTEX_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_INVAL_ALL_MASK 0x00000001U
+#define EUR_CR_MASTER_SLC_CTRL_INVAL_ALL_SHIFT 0
+#define EUR_CR_MASTER_SLC_CTRL_INVAL_ALL_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH 0x4D2C
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_EVENT_MASK 0x00000080U
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_EVENT_SHIFT 7
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_EVENT_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_PIXEL_MASK 0x00000040U
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_PIXEL_SHIFT 6
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_PIXEL_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_VERTEX_MASK 0x00000020U
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_VERTEX_SHIFT 5
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_VERTEX_SIGNED 0
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_MASK 0x00000010U
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_SHIFT 4
+#define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_SIGNED 0
+#define EUR_CR_MASTER_BREAKPOINT_READ 0x4F18
+#define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_SHIFT 4
+#define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_SIGNED 0
+#define EUR_CR_MASTER_BREAKPOINT_TRAP 0x4F1C
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_CONTINUE_SHIFT 1
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_CONTINUE_SIGNED 0
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0
+#define EUR_CR_MASTER_BREAKPOINT 0x4F20
+#define EUR_CR_MASTER_BREAKPOINT_UNTRAPPED_MASK 0x00000008U
+#define EUR_CR_MASTER_BREAKPOINT_UNTRAPPED_SHIFT 3
+#define EUR_CR_MASTER_BREAKPOINT_UNTRAPPED_SIGNED 0
+#define EUR_CR_MASTER_BREAKPOINT_TRAPPED_MASK 0x00000004U
+#define EUR_CR_MASTER_BREAKPOINT_TRAPPED_SHIFT 2
+#define EUR_CR_MASTER_BREAKPOINT_TRAPPED_SIGNED 0
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0 0x4F24
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1 0x4F28
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0
+#define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0
+#define EUR_CR_MASTER_CORE 0x4000
+#define EUR_CR_MASTER_CORE_ENABLE_MASK 0x00000003U
+#define EUR_CR_MASTER_CORE_ENABLE_SHIFT 0
+#define EUR_CR_MASTER_CORE_ENABLE_SIGNED 0
+#define EUR_CR_MASTER_CORE_ID 0x4010
+#define EUR_CR_MASTER_CORE_ID_CONFIG_MULTI_MASK 0x00000001U
+#define EUR_CR_MASTER_CORE_ID_CONFIG_MULTI_SHIFT 0
+#define EUR_CR_MASTER_CORE_ID_CONFIG_MULTI_SIGNED 0
+#define EUR_CR_MASTER_CORE_ID_CONFIG_BASE_MASK 0x00000002U
+#define EUR_CR_MASTER_CORE_ID_CONFIG_BASE_SHIFT 1
+#define EUR_CR_MASTER_CORE_ID_CONFIG_BASE_SIGNED 0
+#define EUR_CR_MASTER_CORE_ID_CONFIG_MASK 0x000000FCU
+#define EUR_CR_MASTER_CORE_ID_CONFIG_SHIFT 2
+#define EUR_CR_MASTER_CORE_ID_CONFIG_SIGNED 0
+#define EUR_CR_MASTER_CORE_ID_CONFIG_CORES_MASK 0x00000F00U
+#define EUR_CR_MASTER_CORE_ID_CONFIG_CORES_SHIFT 8
+#define EUR_CR_MASTER_CORE_ID_CONFIG_CORES_SIGNED 0
+#define EUR_CR_MASTER_CORE_ID_CONFIG_SLC_MASK 0x0000F000U
+#define EUR_CR_MASTER_CORE_ID_CONFIG_SLC_SHIFT 12
+#define EUR_CR_MASTER_CORE_ID_CONFIG_SLC_SIGNED 0
+#define EUR_CR_MASTER_CORE_ID_ID_MASK 0xFFFF0000U
+#define EUR_CR_MASTER_CORE_ID_ID_SHIFT 16
+#define EUR_CR_MASTER_CORE_ID_ID_SIGNED 0
+#define EUR_CR_MASTER_CORE_REVISION 0x4014
+#define EUR_CR_MASTER_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU
+#define EUR_CR_MASTER_CORE_REVISION_MAINTENANCE_SHIFT 0
+#define EUR_CR_MASTER_CORE_REVISION_MAINTENANCE_SIGNED 0
+#define EUR_CR_MASTER_CORE_REVISION_MINOR_MASK 0x0000FF00U
+#define EUR_CR_MASTER_CORE_REVISION_MINOR_SHIFT 8
+#define EUR_CR_MASTER_CORE_REVISION_MINOR_SIGNED 0
+#define EUR_CR_MASTER_CORE_REVISION_MAJOR_MASK 0x00FF0000U
+#define EUR_CR_MASTER_CORE_REVISION_MAJOR_SHIFT 16
+#define EUR_CR_MASTER_CORE_REVISION_MAJOR_SIGNED 0
+#define EUR_CR_MASTER_CORE_REVISION_DESIGNER_MASK 0xFF000000U
+#define EUR_CR_MASTER_CORE_REVISION_DESIGNER_SHIFT 24
+#define EUR_CR_MASTER_CORE_REVISION_DESIGNER_SIGNED 0
+#define EUR_CR_MASTER_SOFT_RESET 0x4080
+#define EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(i) (0x00000001U << (0 + ((i) * 1)))
+#define EUR_CR_MASTER_SOFT_RESET_CORE_RESET_SHIFT(i) (0 + ((i) * 1))
+#define EUR_CR_MASTER_SOFT_RESET_CORE_RESET_REGNUM(i) 0x4080
+#define EUR_CR_MASTER_SOFT_RESET_IPF_RESET_MASK 0x00000010U
+#define EUR_CR_MASTER_SOFT_RESET_IPF_RESET_SHIFT 4
+#define EUR_CR_MASTER_SOFT_RESET_IPF_RESET_SIGNED 0
+#define EUR_CR_MASTER_SOFT_RESET_DPM_RESET_MASK 0x00000020U
+#define EUR_CR_MASTER_SOFT_RESET_DPM_RESET_SHIFT 5
+#define EUR_CR_MASTER_SOFT_RESET_DPM_RESET_SIGNED 0
+#define EUR_CR_MASTER_SOFT_RESET_VDM_RESET_MASK 0x00000040U
+#define EUR_CR_MASTER_SOFT_RESET_VDM_RESET_SHIFT 6
+#define EUR_CR_MASTER_SOFT_RESET_VDM_RESET_SIGNED 0
+#define EUR_CR_MASTER_SOFT_RESET_SLC_RESET_MASK 0x00000080U
+#define EUR_CR_MASTER_SOFT_RESET_SLC_RESET_SHIFT 7
+#define EUR_CR_MASTER_SOFT_RESET_SLC_RESET_SIGNED 0
+#define EUR_CR_MASTER_SOFT_RESET_BIF_RESET_MASK 0x00000100U
+#define EUR_CR_MASTER_SOFT_RESET_BIF_RESET_SHIFT 8
+#define EUR_CR_MASTER_SOFT_RESET_BIF_RESET_SIGNED 0
+#define EUR_CR_MASTER_SOFT_RESET_MCI_RESET_MASK 0x00000200U
+#define EUR_CR_MASTER_SOFT_RESET_MCI_RESET_SHIFT 9
+#define EUR_CR_MASTER_SOFT_RESET_MCI_RESET_SIGNED 0
+#define EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_MASK 0x00000400U
+#define EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_SHIFT 10
+#define EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_SIGNED 0
+
+#endif
+
generated by cgit v1.1 at 2025-03-23 20:52:46 +0000