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* gpu: ion: check for input arguments in ion_freeSuman Anna2014-10-011-0/+2
| | | | | | | | | | ion_free is a public API and is directly dereferencing a pointer without checking for NULL. A check has been added for the same and throws a WARN in case of invalid arguments. Change-Id: Idcf72e4449f8cba2b8342d6fb0f64600c2c59c7e Signed-off-by: Suman Anna <s-anna@ti.com>
* OMAP: TILER: validate input width and heightAndy Gross2014-10-011-12/+17
| | | | | | | | | | Add validation of input width and height to ensure that it does not exceed maximum pixel width and height for the specific format. Validate maximum length for 1D allocations. Change-Id: I64b00f93a312ae715a040da28a0b0fe663afa9d8 Signed-off-by: Andy Gross <andy.gross@ti.com>
* rpmsg: omx: initialize completion event in rpmsg_omx_openJuan Gutierrez2014-10-011-2/+2
| | | | | | | | | | | | | | | | | | An omx object is created when opening the rpmsg-omx device. However the "reply_arrived" completion event is not initialized until the connection message is sent across. When the rpmsg_omx driver is removed (like in recovery), all pending threads waiting on the "reply_arrived" are unblocked by a complete_all call, however, if the rpmsg-omx device was only opened, such event is not initialized yet, so the complete_all call will dereference a null object causing a panic. This patch moves the initialization of the "reply_arrived" completion event to the open call, after the allocation of the omx object. Change-Id: I92cf9cf5ac748456cb43bedc88fe1a8d80addd6c Signed-off-by: Juan Gutierrez <jgutierrez@ti.com>
* rpmsg: omx: send disconnect only if omx state is connectedMiguel Vadillo2014-10-011-16/+19
| | | | | | | | | The rpmsg_omx driver sends a disconnect message automatically when the driver's .release is called. This should be done only if a connection has been established, otherwise just destroy the local end point. Change-Id: I21b84aa6d91ae0d456f49cbe958f8e64caf691d5 Signed-off-by: Miguel Vadillo <vadillo@ti.com>
* rpmsg: omx: fix copy_to_user in register/unregister ioctlsSuman Anna2014-10-011-3/+5
| | | | | | | | | | | | | The ION fd registration and deregistration ioctls has the arguments reversed in the copy_to_user() calls. The same has been fixed. Also included a minor additional case for returning a NULL ION handle back to user-space. Change-Id: I9d45957f9b913fa1775e70618f0da82e914a41d6 Signed-off-by: Tyler Luu <tluu@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
* omap: Add TILER reservation ION heap to omap4 board fileDavid Schleef2014-10-011-2/+7
| | | | | | | | | | | | registration gives ion clients access to tiler reservation heap The tiler reservation heap is for allocating TILER address space, but not the underlying pages. The idea is to allocate TILER address space and one or more ION buffers from the system heap, and map system heap buffers into the allocated TILER address space. Signed-off-by: David Schleef <ds@ti.com> Change-Id: I3eb8125d604106185c37f75d61cbbd9f2ef175a1
* omap: Add ION system heap to omap board fileDavid Schleef2014-10-012-2/+7
| | | | | | | | gives ion clients access to system heap for allocation instead of being restricted to pre-allocated carveouts Change-Id: I560e7b8cda1b561d737b9c5bc427b5cbf2591731 Signed-off-by: David Schleef <ds@ti.com>
* ion: fix comment to match realityDavid Schleef2014-10-011-1/+1
| | | | | Change-Id: Ib722e6c34965bf48ca5bdaaef3b4741146cc1508 Signed-off-by: David Schleef <ds@ti.com>
* ion: add support for tiler reservation heapDavid Schleef2014-10-013-61/+118
| | | | | | | | | | | | | The tiler reservation heap is for allocating TILER address space, but not the underlying pages. The idea is to allocate TILER address space and one or more ION buffers from the system heap, and map system heap buffers into the allocated TILER address space. Change-Id: Ibd53ab811259cabec87384cf2ab4f99c0cbdca23 Signed-off-by: David Schleef <ds@ti.com> Conflicts: drivers/gpu/ion/omap/omap_tiler_heap.c
* ion: convert system heap to alloc_page()David Schleef2014-10-011-30/+74
| | | | | | | | | | vmalloc() allocates pages and maps them into kernel space. If nobody requires the area to be mapped in kernel space, this uses potentially valuable VM address space. Split into separate allocation and mapping of pages. Change-Id: I98411b93edea67c2068e20b5e48708fb38a4cd1f Signed-off-by: David Schleef <ds@ti.com>
* OMAP4: PM: IVA AUTO RET relaxed workaround in idle pathCedric Vamour2014-10-011-9/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AUTO RET for IVA VDD Cannot be permanently enabled during OFF mode due to potential race between IVA VDD entering RET and start of Device OFF mode. It is mandatory to have AUTO RET for IVA VDD exlusive with Devide OFF mode. In order to avoid lockup in OFF mode sequence, system must ensure IVA voltage domain transitions straight from stable ON to OFF. In addition, management of IVA VDD SmartReflex sensor at exit of idle path may introduce a misalignment between IVA Voltage Controller state and IVA PRCM voltage FSM based on following identified scenario: IVA Voltage Controller is woken-up due to SmartReflex management while IVA PRCM voltage FSM stays in RET in absence of any IVA module wake-up event (which is not systematic in idle path as opposed to MPU and CORE VDDs being necessarily woken up with MPU and CORE PDs). WA involves: Ensure stable ON-OFF transition for IVA voltage domain during OFF mode sequence. Ensure VCON and PRCM FSM are kept aligned due to IVA SR handling in idle path. 1) AUTO RET for IVA VDD is enabled entering in idle path, disabled exiting idle path and IVA VDD is always woken-up with a SW dummy wakeup. 2) OFF mode is enabled only in Suspend path. 3) AUTO RET for IVA VDD remains disabled in Suspend path (before OFF mode). REVISIT: Update the patch once proper Errata is out for 44xx. Benefits: 1) This patch ensures it is possible to gate SYS_CLK during OS-Idle LCD OFF when all domains are idled, saving up to 2mA at VBAT from external clock buffer. 2) IVA voltage domain is now allowed to scale to Retention during idle which reduces power consumption on all types of use case allowing extensive use of idle path (e.g.: Home screen, Page reading). Effects are especially visible if system uses Smart-Reflex Class 1.5 compared to Class 3 considering the increased difference of voltage from converged Voltage SR vs Retention voltage. TODO: quantify the actual savings from IVA-RET with further measurements. Change-Id: I01f0431f7556f0baf0b5b6b42092cd11c2442f00 Signed-off-by: Cedric Vamour <c-vamour@ti.com>
* OMAPDSS: drop small YUV encoded frames on OMAP44xxSergiy Kibrik2014-10-011-0/+15
| | | | | | | | | | OMAP44xx has hardware limitation: in stall mode, when the frame pixel size is less than output SyncFifo depth(16), DISPC hangs without sending any data. Simple workaround is to drop such frame, as cases when YUV frames of this size are very rare. Change-Id: I31dc262b07a52b66209c093f136ad2bac66f9439 Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
* ION: Added support for getting ion phys without clientSunita Nadampalli2014-10-012-0/+74
| | | | | | | | | | | In order to dereference the ion_handles passed from user side to kernel, there should be support for api without client identity. This patch adds this support. Change-Id: I95d0d460c9e0ad202d14e7620b82e1fa9d48f746 Signed-off-by: Sunita Nadampalli <sunitan@ti.com> Signed-off-by: Lajos Molnar <lajos@ti.com> Signed-off-by: Dima Svetlov <svetlov@ti.com>
* Revert "OMAPDSS: Increase PLL1_CLK1 frequency for correct work with large ↵Dima Svetlov2014-10-011-6/+6
| | | | | | | | | panels" This reverts commit 1fe611b1c2eea594ed3738d50bfb37a701d2632c. Change-Id: I444e0e09a99ce5f495ffc298d388678e0e07cda4 Signed-off-by: Dima Svetlov <svetlov@ti.com>
* OMAPDSS: MFlag thresholds settingsSunita Nadampalli2014-10-011-1/+9
| | | | | | | | | | | As per the simultaion team suggestion, the below thesholds are set: HT = fifosize * 5/8; LT = fifosize * 4/8; Change-Id: Ieef7d8a090e38ce717729fe30f60f46c6dfd6ddd Signed-off-by: Sunita Nadampalli <sunitan@ti.com> Signed-off-by: Lajos Molnar <lajos@ti.com> Signed-off-by: Dima Svetlov <svetlov@ti.com>
* Input: Add driver for Cypress touchpanelsPeter Nordström2014-10-018-0/+9749
| | | | | | | | | Supports CY8CTMA398 & CY8CTMA884 Change-Id: Ifcdba380e3a8712716054dd6c5d807ebb2c1beb6 Signed-off-by: Peter Nordström <nordstrom@ti.com> Signed-off-by: Lajos Molnar <lajos@ti.com> Signed-off-by: Dima Svetlov <svetlov@ti.com>
* OMAPDSS: DISPC: fix pclk divisor limitsSergiy Kibrik2014-10-011-2/+35
| | | | | | | | | | | | | | According to TRM, minimal pixel clock divisor value can be 1. Fix corresponding checks, as high resolution panels use undivided pixel clock frequency. Also certain scaler unit constraint must be met: in case DISPC_CLK and pixel clock frequencies are equal, set IPC to work on rising edge. Change-Id: Iabeac2ad81f6909213cb81f4e16b1d0762369b53 Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com> Signed-off-by: Lajos Molnar <lajos@ti.com> Signed-off-by: Dima Svetlov <svetlov@ti.com>
* omap: rpmsg: bump to max freq while booting remote processorMiguel Vadillo2014-10-012-1/+58
| | | | | | | | | | | | | | | | | | | | | | | | Reduce the remote processor booting time by bumping to the max frequency. This is achieved by putting in constraints before the loading of the remote processor. The latter is known through the RPROC_PRELOAD notification. Once the remote processor has reached a certain point, it would send a message, RP_MSG_BOOTINIT_DONE via mailbox to notify the host that the remote processor has completed the basic boot and initization. The constraints are released upon receipt of this message. They are also released in case of an error during loading. NOTE: The current implementation used tput api for ipu since freq scale api is not supported directly yet. Change-Id: I1fe936087f00872756c7b532ee58d923e695ff28 Signed-off-by: Miguel Vadillo <vadillo@ti.com> Signed-off-by: Fernando Guzman Lugo <fernando.lugo@ti.com> Signed-off-by: Subramaniam C.A <subramaniam.ca@ti.com> Signed-off-by: Chandra Sekhar.Anagani <chandu@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
* remoteproc: add a notify event for firmware preloadChandra Sekhar.Anagani2014-10-012-0/+8
| | | | | | | | | | | Added a new rproc event, RPROC_PRELOAD, to send a notification about commencement of loading of a image into remoteproc's memory. This event will currently be used for bumping up the remoteproc frequency to optimize the overall boot time of the remote processor. Change-Id: I7e36e54fe938b3242b9e87fd33d6e190a1233083 Signed-off-by: Chandra Sekhar.Anagani <chandu@ti.com>
* rpmsg: omx: return ENXIO in rpmsg_omx_writeVidhoon Viswanathan2014-10-011-0/+3
| | | | | | | | | | | | | | | The error code, ENXIO is used in rpmsg_omx driver to indicate a terminal error on the remote processor side. This status is maintained during the recovery of the remote processor, while the cdev gets reinitialized/recreated. The rpmsg_omx's write file operation is currently not returning this error. This has been added now to have it behave in the same way as the read file operation. Change-Id: I61d6e6c07aa39208d913da622ed32d809c51d409 Signed-off-by: Vidhoon Viswanathan <vidhoon@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
* remoteproc: fix obsolete comment about memory_mapsDavid Schleef2014-10-011-1/+0
| | | | | | | | | | memory_maps in remoteproc platform data has been replaced with memory_pool, but the comment still remained. It has been cleaned up. Change-Id: Iae78c0b8e8d4caccce2fc0248b89a9d18f8d7cca Signed-off-by: David Schleef <ds@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
* rpmsg: omx: copy_from_user() errors should return -EFAULTDavid Schleef2014-10-011-1/+1
| | | | | Change-Id: Ib4a2d92dd3b8afa18e60019871cfea2e6b446a4d Signed-off-by: David Schleef <ds@ti.com>
* OMAP2PLUS:fix for TF doesn't work when CPU1 on/offEugen Mandrenko2014-10-011-2/+3
| | | | | | | | | | | | | TI thermal framework: rework initialization sequence The initialization of max_thermal was placed in function which is executed for each CPU1 start. The old value of max_thermal is lost in this case and is set to max_freq. As result, the omap_thermal_step_freq_down() can't reduce the frequency if CPU1 is switched on/off often. Signed-off-by: Eugen Mandrenko <ievgen.mandrenko@ti.com> Change-Id: Idcbc6a56407595b8f71743b91d994990a279593b
* ARM: OMAP4: Initialize the cooling level properlyDan Murphy2014-10-011-1/+1
| | | | | | | | Initialize the cooling level properly to 0 since at init the device is at max frequency Change-Id: I69c0ba6ca5a2f5490b0afeb4fec2e9dbd1a0a18b Signed-off-by: Dan Murphy <dmurphy@ti.com>
* sched: Fix select_fallback_rq() vs cpu_active/cpu_onlinePeter Zijlstra2014-10-013-37/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 5fbd036b55 ("sched: Cleanup cpu_active madness"), which was supposed to finally sort the cpu_active mess, instead uncovered more. Since CPU_STARTING is ran before setting the cpu online, there's a (small) window where the cpu has active,!online. If during this time there's a wakeup of a task that used to reside on that cpu select_task_rq() will use select_fallback_rq() to compute an alternative cpu to run on since we find !online. select_fallback_rq() however will compute the new cpu against cpu_active, this means that it can return the same cpu it started out with, the !online one, since that cpu is in fact marked active. This results in us trying to scheduling a task on an offline cpu and triggering a WARN in the IPI code. The solution proposed by Chuansheng Liu of setting cpu_active in set_cpu_online() is buggy, firstly not all archs actually use set_cpu_online(), secondly, not all archs call set_cpu_online() with IRQs disabled, this means we would introduce either the same race or the race from fd8a7de17 ("x86: cpu-hotplug: Prevent softirq wakeup on wrong CPU") -- albeit much narrower. [ By setting online first and active later we have a window of online,!active, fresh and bound kthreads have task_cpu() of 0 and since cpu0 isn't in tsk_cpus_allowed() we end up in select_fallback_rq() which excludes !active, resulting in a reset of ->cpus_allowed and the thread running all over the place. ] The solution is to re-work select_fallback_rq() to require active _and_ online. This makes the active,!online case work as expected, OTOH archs running CPU_STARTING after setting online are now vulnerable to the issue from fd8a7de17 -- these are alpha and blackfin. Change-Id: I34bedb461f77bfe4af78ef5ddd3fb3a230ca3551 Reported-by: Chuansheng Liu <chuansheng.liu@intel.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Frysinger <vapier@gentoo.org> Cc: linux-alpha@vger.kernel.org Link: http://lkml.kernel.org/n/tip-hubqk1i10o4dpvlm06gq7v6j@git.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Taras Kondratiuk <taras@ti.com>
* sched: Cleanup cpu_active madnessPeter Zijlstra2014-10-013-24/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stepan found: CPU0 CPUn _cpu_up() __cpu_up() boostrap() notify_cpu_starting() set_cpu_online() while (!cpu_active()) cpu_relax() <PREEMPT-out> smp_call_function(.wait=1) /* we find cpu_online() is true */ arch_send_call_function_ipi_mask() /* wait-forever-more */ <PREEMPT-in> local_irq_enable() cpu_notify(CPU_ONLINE) sched_cpu_active() set_cpu_active() Now the purpose of cpu_active is mostly with bringing down a cpu, where we mark it !active to avoid the load-balancer from moving tasks to it while we tear down the cpu. This is required because we only update the sched_domain tree after we brought the cpu-down. And this is needed so that some tasks can still run while we bring it down, we just don't want new tasks to appear. On cpu-up however the sched_domain tree doesn't yet include the new cpu, so its invisible to the load-balancer, regardless of the active state. So instead of setting the active state after we boot the new cpu (and consequently having to wait for it before enabling interrupts) set the cpu active before we set it online and avoid the whole mess. Change-Id: Ibad68784d481672eed23b0e8ad1d5fefc8755bd7 Reported-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1323965362.18942.71.camel@twins Signed-off-by: Ingo Molnar <mingo@elte.hu> [taras@ti.com: backported from v3.4-rc1] Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAPDSS: DSSCOMP: Export dsscomp_set_platform_dataLajos Molnar2014-10-011-0/+4
| | | | | | | | | This is used by android-display to set up default tiler1d slot size. Change-Id: Ic6fe49b9338d8ce41c2ac2b444d8ef018ee5fc7a Signed-off-by: Lajos Molnar <lajos@ti.com> Signed-off-by: Dima Svetlov <svetlov@ti.com>
* gpu: ion: omap: Set correct heap for TILER allocationsLajos Molnar2014-10-011-0/+1
| | | | | | | | | | | OMAP has two TILER heaps, but all allocations are logged under the first TILER heap, as ion_alloc only takes a heap type mask. Correct the heap after ion_alloc, so the buffer is maintained under the correct heap. Change-Id: I7b4eb690a6cde6f07632f5254c91374c6088cb8a Signed-off-by: Lajos Molnar <lajos@ti.com> Signed-off-by: Dima Svetlov <svetlov@ti.com>
* gpu: ion: group heap allocations by id in the debugfsLajos Molnar2014-10-011-4/+4
| | | | | | | | | | Multiple ion heaps can have the same type. These heaps will have separate debugfs files, but any allocation for a heap with the same type will be listed in them. Change-Id: Iad2f660c539e151d62e76f8f99ecc9ad80b16dd5 Signed-off-by: Lajos Molnar <lajos@ti.com> Singed-off-by: Dima Svetlov <svetlov@ti.com>
* TILER: Add tiler_backpages methodLajos Molnar2014-10-012-11/+63
| | | | | | | | | | | | tiler_backpages method can be used to get the number of pages required for a tiler allocation. This method is called before the memory is partitioned, therefore, we cannot rely on tiler being initialized. Separated geometry initialization for this purpose. Change-Id: Ia68cbd81c31a357fdc51036753db222d21994996 Signed-off-by: Lajos Molnar <lajos@ti.com> Signed-off-by: Dima Svetlov <svetlov@ti.com>
* omap2plus: cpufreq: Modify lpj recalculation logicSergii Postulga2014-10-011-26/+37
| | | | | | | | | | | | | | | | | | | | Somethimes "mdelay" function provide delay that several times shorter than it should be. This happens because recalculating lpj performed after switching OPP. In this case, for short period of time, when OPP on MPU was switched but lpj was not recalculated, "udelay" function can provide incorrect delay - upto 5 times shorter (if OPP was switched from lowest to highest). This patch changes lpj recalculation logic to: if OPP will be switched to higher - recalculate lpj before switching OPP, if OPP will be switched to lower - recalculate lpj after switching OPP. Change-Id: I3258e756c471fd0258a849d712ab00f4e1279ea9 Signed-off-by: Sergii Postulga <x0153364@ti.com>
* OMAP4: IRQ: Fix OMAP44XX_IRQ_CPUIDLE_POKE0 definitionGrygorii Strashko2014-10-011-1/+1
| | | | | | | | | | | According to OMAP4470 TRM the MA_IRQ_60 is busy for L3_STAT_ALARM_IRQ L3 NoC statistics collector alarm interrupt. The MA_IRQ_106 is reserved in all OMAP4 chips, so it's selected for using as OMAP44XX_IRQ_CPUIDLE_POKE0. Change-Id: Iba7f727035c71db009defe684a66fb8c58ee3f93 Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
* gcx: fixed error handling.Alexei Shlychkov2014-10-013-24/+72
| | | | | Change-Id: I4e38c35b51fbff71f2f9070e67478ebb726c3c4a Signed-off-by: Alexei Shlychkov <shlychkov@gmail.com>
* gcx: fixed color conversion table.Alexei Shlychkov2014-10-011-61/+89
| | | | | Change-Id: I9f0c8ed5f6a341ca8d6a2460a1b5225d78a505e4 Signed-off-by: Alexei Shlychkov <shlychkov@gmail.com>
* OMAP4: PM: Add errata id for handling Errata i745Eugen Mandrenko2014-10-011-10/+6
| | | | | | | | The errata handler is present in kernel 3.0. The patch adds the Errata id for simplification of search in the kernel sources Change-Id: I251c0bd09754e5af9ec40c01c50e24e25eba9227 Signed-off-by: Eugen Mandrenko <ievgen.mandrenko@ti.com>
* OMAP4: EMIF: unify access to EMIF_PWR_MGMT_CTRL.REG_LP_MODEGrygorii Strashko2014-10-011-14/+5
| | | | | | | Use set_lp_mode for changing EMIF_PWR_MGMT_CTRL.REG_LP_MODE. Change-Id: Ia6410f97c8937faee6fbfc335d5d1158de41583b Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
* ALSA: pcm: export 'snd_interval_step' symbolMisael Lopez Cruz2014-10-012-1/+4
| | | | | | | | Export 'snd_interval_step' symbol so that ALSA drivers can use it to add hw rules. Change-Id: Ic7d38683a46d281db9b1a36a5d5eabdb92876153 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* MFD: twl6040-codec: Change power-up verification policyMisael Lopez Cruz2014-10-011-8/+9
| | | | | | | | | | | | | | | | | | | | | Automatic power-up completion result can be affected by race conditions between the completion task itself and the READYINT handler, leading to false power-up failures as the completion timeout may expire before READYINT handler gets executed and marks completion. Instead, the first verification for a successful power-up sequence is the expected state of NCPCTL, LDOCTL and LPPLLCTL registers. These registers will have specific values after automatic power-up sequence has completed. False power-up success is still checked, this is the case where the READYINT is received but the hardware state is not consistent with what is known/expected after a successful sequence. Under these circumstances, we retry automatic power-up. Change-Id: I9f85d67a10e84564a38f7d97a78345be06ac3b16 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* MFD: twl6040-codec: Refactor power-on verificationMisael Lopez Cruz2014-10-011-32/+41
| | | | | | | | | Refactor power-on verification which consists of checking NCPCTL, LDOCTL and LPPLLCTL registers against expected values of successful automatic power-up sequences. Change-Id: I20c0693922baa6700a117881c47cbf400716446b Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: OMAP ABE: Update to release 09.56Sebastien Guiriec2014-10-0115-490/+721
| | | | | | | | | | | | | Update ABE firmware to 09.56. This firmware has the next update: - Add MONO 16 bits support - Update SRC 48->96 kHz. - Enable 4/16/48 kHz on Voice port and BT. - Enable DL1 path to Handsfree path - Add new filter functions for DMIC Change-Id: Idbc527887b8cbd97ea1882562763950c6144add2 Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com>
* gc320: determine whether context was lost and reset gpuTony Lofthouse2014-10-014-3/+19
| | | | | | | | | If the context is lost this means BB2D_RST is asserted and we will need to take appropriate action. This assumes that resetting the GPU is the limit of this. There could be more. Change-Id: I71ec274e6dd46d0b22c0b1f708eaa3303bef824d Signed-off-by: Tony Lofthouse <a0741364@ti.com>
* gcx: fixed surface comparison and surface parameter validation.Alexei Shlychkov2014-10-011-122/+195
| | | | | Change-Id: I49065cb1262f8bf5beb4c3ed068cc81d6bda8555 Signed-off-by: Alexei Shlychkov <shlychkov@gmail.com>
* gcx: driver cleanup; fixed debug printing; dumping improvement.Alexei Shlychkov2014-10-016-174/+37
| | | | | Change-Id: If875cf055c2904be498b8c15652d5eb3798bc919 Signed-off-by: Alexei Shlychkov <shlychkov@gmail.com>
* OMAP4: PM: cold reset: wrong value is used to set LOGICRETSTATEGrygorii Strashko2014-10-012-1/+7
| | | | | | | | | | | The size of LOGICRETSTATE field is 1 bit, and pwrdm_set_logic_retst() can accept only PWRDM_POWER_RET(0x1)/PWRDM_POWER_OFF(0x0) values. Additional check of "pwrst" parameter and print out of error message added in pwrdm_set_logic_retst() to minimize such issues in future. Change-Id: I413e1e2ba3823574d4450225ed30cffb2cdfd565 Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
* OMAP4: SAR: WA overwrite L3INIT CD mode to SW_SLEEP(1) in SARArthur Cassegrain2014-10-011-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | The wrong value of CM_L3INIT_CLKSTCTRL.CLKTRCTRL = 2 (SW_WKUP) has been stored in SAR during omap4_sar_save() execution and causes power over consumption on OFF mode due to C2C operation. It happens because the L3INIT CD need to be enabled during omap4_sar_save() execution for proper USBHOST module context storing. Problematic use case: 1) OMAP goes to sleep, 2) modem wakeup the C2C, the EMIF but the MPU is still sleeping (as expected) 3) Modem release all his constraints, C2C is turned to OFF. 4) but OMAP never reach again OFF while we don't wakeup the CPU (by a keypress for example), sys_clk is already ON and voltages are not equal to 0. (OPP 50 for CORE_3 and retention voltages for both VCORE1 and VCORE2). As WA overwrite CM_L3INIT_CLKSTCTRL.CLKTRCTRL = 0x1 (SW_SLEEP). Change-Id: I2e453c07f61bab28a7213dd66044fd41a021961b Signed-off-by: Arthur Cassegrain <a-cassegrain@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
* OMAPDSS: DSSCOMP: efficiency improvement.Mykhailo Denysiuk2014-10-012-19/+84
| | | | | | | | | | | | | This change adds 3 local caches of objects, which are used at each flip buffer action. In original variant kzalloc()/kfree() functions are called each time dsscomp_gralloc_queue() function is called. This meens that slab|slob|slub common cache is used at each frame draw action. Call to kzalloc()/kfree() result in synchronization with other code, which uses common cache, and can result in dips in FPS, when other code allocates/frees memory. This change improves reliability, autonomy and efficiency of DSSCOMP module. Change-Id: Id50778f4579309fb71318a32820b9d6441a6dac1 Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
* ARM: OMAP4: USB: Update workaround for USB errata i719Jon Hunter2014-10-015-38/+57
| | | | | | | | | | | | | | | | | Due to USB errata i719 the USB host save-and-restore context can be corrupted if the device enters off mode more than two times without enabling the USB host controller in between. The corruption is occuring during the software save of the USB context which occurs on entry to every off mode attempt. To avoid this problem only save the USB context if the USB host controller has been enabled since the previous off mode attempt. We do not need to save the USB context on every entry to off mode if the USB controller has not been enabled. Change-Id: I67e07963679af6494ef289eb10db09c0162d6f00 Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Volodymyr Riazantsev <v.riazantsev@ti.com> Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* OMAP4: DSS: Implement workaround for Errata ID:i733.Mykhailo Denysiuk2014-10-011-23/+39
| | | | | | | | | | | | | | | | | | | | | Description of Errata i733: Due to wrong timings, all register accesses transitioning through the L4 interconnect toward DSS are not reliable. Workaround: DSS register access should be addressed through the L3 interconnect. This change fixes errata by using L3 for access to DSS in dss_hwmod instead of L4. Silicon Versions Impacted: OMAP4430 ES1.0, ES2.0, ES2.1, ES2.2, ES2.3 OMAP4460 ES1.0, ES1.1 OMAP4470 ES1.0 Change-Id: Ie087b861ee653a3beeacba74c3afe7b1a0490ed4 Co-author: Raghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
* OMAP: EMIF: fix LP_MODE_PWR_DN value definitionAndrii Tseglytskyi2014-10-011-1/+1
| | | | | | | | According to TRM the EMIF Power-down mode is identified by value 0x4 (EMIF_PWR_MGMT_CTRL.REG_LP_MODE) Change-Id: I4d9b9534dea27ab4619af5b6d78de8ab14f0fead Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
* OMAP:MUSB:OTG: Disable MUSB DMA mode incase of DMA channel request failureMantesh Sarasetti2014-10-011-0/+5
| | | | | | | | | | | | | Currently in case of MUSB DMA channel request failure we are not clearing MUSB_RXCSR_DMAENAB, MUSB_RXCSR_H_AUTOREQ and MUSB_RXCSR_AUTOCLEAR bits of MUSB RXCSR of MUSB DMA. Which is causing failure in receipt of data packets in next transfer. Fix is to disable the MUSB DMA mode and related bits incase of DMA channel request fails Change-Id: Ie6caed6ef2a01ef647cc839c01724be32a247598 Signed-off-by: Mantesh Sarashetti <mantesh@ti.com>
generated by cgit v1.1 at 2025-03-26 02:53:19 +0000