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path: root/include/asm-mips/cpu.h
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* [MIPS] Convert list of CPU types from #define to enum.Ralf Baechle2007-10-111-70/+49
* [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle2007-10-111-18/+17
* [MIPS] Add support for BCM47XX CPUs.Aurelien Jarno2007-10-111-2/+10
* [MIPS] PMC MSP71xx mips commonMarc St-Jean2007-07-101-0/+2
* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-101-1/+6
* [MIPS] Enable support for the userlocal hardware registerRalf Baechle2007-07-101-0/+1
* [MIPS] Add macros to encode processor revisions.Ralf Baechle2007-07-061-0/+11
* [MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle2006-07-131-1/+1
* [MIPS] Treat R14000 like R10000.Kumba2006-06-011-1/+3
* [MIPS] Fix detection and handling of the 74K processor.Chris Dearman2006-06-011-1/+3
* [MIPS] Fix CPU type bitmasks for MIPS III, IV and V.Maciej W. Rozycki2006-02-141-3/+3
* MIPS: Reorganize ISA constants strictly as bitmasks.Ralf Baechle2006-01-101-7/+10
* MIPS: Introduce machinery for testing for MIPSxxR1/2.Ralf Baechle2006-01-101-1/+3
* MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle2006-01-101-10/+7
* Add support for SB1A CPU.Andrew Isaacson2005-10-291-1/+3
* Cleanup the mess in cpu_cache_init.Ralf Baechle2005-10-291-19/+21
* Move MIPS Technologies processor IDs to where they belong.Maciej W. Rozycki2005-10-291-2/+7
* Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov2005-10-291-1/+3
* Detect the MIPS R2 vectored interrupt, external interrupt controllerRalf Baechle2005-10-291-0/+4
* Detect the 34K.Ralf Baechle2005-10-291-1/+3
* Support the MIPS32 / MIPS64 DSP ASE.Ralf Baechle2005-10-291-0/+2
* Cleanup decoding of MIPSxx config registers.Ralf Baechle2005-10-291-1/+9
* Base Au1200 2.6 support.Pete Popov2005-10-291-1/+2
* Add a few more PrId vendor IDs.Ralf Baechle2005-10-291-6/+11
* Linux-2.6.12-rc2Linus Torvalds2005-04-161-0/+222
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