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author | Andrew Hsieh <andrewhsieh@google.com> | 2013-09-06 18:37:46 +0800 |
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committer | Andrew Hsieh <andrewhsieh@google.com> | 2013-09-06 19:04:40 +0800 |
commit | 6986c6e7f06bb3bdedfc3bb08694da9b1227048c (patch) | |
tree | 5c0f01f1f54d9040100858182232c1fb4134b58f /9/platforms/android-18/arch-mips/usr/include/asm/mips-boards/generic.h | |
parent | 30ee84f92cb832c789366c516fcadb718ccc25e8 (diff) | |
download | prebuilts_ndk-6986c6e7f06bb3bdedfc3bb08694da9b1227048c.zip prebuilts_ndk-6986c6e7f06bb3bdedfc3bb08694da9b1227048c.tar.gz prebuilts_ndk-6986c6e7f06bb3bdedfc3bb08694da9b1227048c.tar.bz2 |
Add NDK r9 part 1/2: platforms/
Change-Id: Ie572e90ffda7f982d931dda1a9f5a0c68953a762
Diffstat (limited to '9/platforms/android-18/arch-mips/usr/include/asm/mips-boards/generic.h')
-rw-r--r-- | 9/platforms/android-18/arch-mips/usr/include/asm/mips-boards/generic.h | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/9/platforms/android-18/arch-mips/usr/include/asm/mips-boards/generic.h b/9/platforms/android-18/arch-mips/usr/include/asm/mips-boards/generic.h new file mode 100644 index 0000000..fe07137 --- /dev/null +++ b/9/platforms/android-18/arch-mips/usr/include/asm/mips-boards/generic.h @@ -0,0 +1,66 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __ASM_MIPS_BOARDS_GENERIC_H +#define __ASM_MIPS_BOARDS_GENERIC_H +#include <asm/addrspace.h> +#include <asm/byteorder.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#include <asm/mips-boards/bonito64.h> +#define ASCII_DISPLAY_WORD_BASE 0x1f000410 +#define ASCII_DISPLAY_POS_BASE 0x1f000418 +#define YAMON_PROM_PRINT_ADDR 0x1fc00504 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SOFTRES_REG 0x1f000500 +#define GORESET 0x42 +#define MIPS_REVISION_REG 0x1fc00010 +#define MIPS_REVISION_CORID_QED_RM5261 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MIPS_REVISION_CORID_CORE_LV 1 +#define MIPS_REVISION_CORID_BONITO64 2 +#define MIPS_REVISION_CORID_CORE_20K 3 +#define MIPS_REVISION_CORID_CORE_FPGA 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MIPS_REVISION_CORID_CORE_MSC 5 +#define MIPS_REVISION_CORID_CORE_EMUL 6 +#define MIPS_REVISION_CORID_CORE_FPGA2 7 +#define MIPS_REVISION_CORID_CORE_FPGAR2 8 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MIPS_REVISION_CORID_CORE_FPGA3 9 +#define MIPS_REVISION_CORID_CORE_24K 10 +#define MIPS_REVISION_CORID_CORE_FPGA4 11 +#define MIPS_REVISION_CORID_CORE_FPGA5 12 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MIPS_REVISION_CORID_CORE_EMUL_BON -1 +#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 +#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) +#define MIPS_REVISION_SCON_OTHER 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MIPS_REVISION_SCON_SOCITSC 1 +#define MIPS_REVISION_SCON_SOCITSCP 2 +#define MIPS_REVISION_SCON_UNKNOWN -1 +#define MIPS_REVISION_SCON_GT64120 -2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MIPS_REVISION_SCON_BONITO -3 +#define MIPS_REVISION_SCON_BRTL -4 +#define MIPS_REVISION_SCON_SOCIT -5 +#define MIPS_REVISION_SCON_ROCIT -6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) +#define mips_pcibios_init() do { } while (0) +#endif |