| Commit message (Collapse) | Author | Age | Files | Lines |
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for 32-bit, remove Atom caches sizes for 64-bit, fix license.
Change-Id: Ieda6367d7b21cf25b2beda6dd8d77cf668d3f2af
Signed-off-by: Varvara Rainchik <varvara.rainchik@intel.com>
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Adds Silvermont specific cache sizes for memset16/32 SSE optimization.
Change-Id: Ib5ea086d57544e74ac384ee1ef516b8511392f70
Signed-off-by: Henrik Smiding <henrik.smiding@intel.com>
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Change-Id: Ieb72af8cf7f93210a68a87b1e2538deb5642f4d5
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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ARCH_X86_HAVE_SSE2 is always true
Change-Id: I680493d14280aafad5448aec727e8d9a84a6db00
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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Change-Id: Ife2dd406e1dcb962e5e97788c515ac96f5c52e44
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