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* Remove dead code.Elliott Hughes2014-12-032-124/+0
| | | | | | | | | | Intel accidentally made this dead code in 2010 with commit 2bef93cc20155c3a59cdbb22c564c4b385b2c160, and no one's ever noticed. Since no one noticing for so long implies that it doesn't matter, let's just kill the supposedly optimized code. Change-Id: Id5b37056cb8884c20bfe2db362e19b46f02e337d
* Fix some clang compilation issues.Dan Albert2014-09-111-2/+2
| | | | | | | | | | | | Use expected inline behavior with clang. GCC defaults to -std=gnu90, giving C89 inline semantics with GNU extensions. Clang defaults to C99. Explicitly use gnu90. Mark an unused parameter as __unused. Fix some incorrect casts. Change-Id: I05b95585d5e3688eda71769b63b6b8a9237bcaf4
* pixelflinger: Use pointer arithmetic to determine cache flush parametersAshok Bhat2014-06-191-3/+3
| | | | | | | | | CodeCache casts base address to long and then adds size (of type ssize_t) to get end address. This can cause sign-extension problems. This patch instead uses simple pointer arithmetic. Change-Id: Ib71d515a6fd6a7f4762cf974d6cf4eba9a601fa8 Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
* Judge mmap failed by MAP_FAILED instead of NULLHurri Lu2014-05-221-1/+1
| | | | | Change-Id: I74422cfdba341fcd1a6235044700cf3986e853d0 Signed-off-by: Hurri Lu <jlu32@marvell.com>
* Cleanup: warning fixit.Sasha Levitskiy2014-04-112-12/+7
| | | | | | | bootable/recovery has a dependent commit: I9adb470b04e4301989d128c9c3097b21b4dea431 Change-Id: Icf23e659265d71d5226d527c2b40cfbc132320ee Signed-off-by: Sasha Levitskiy <sanek@google.com>
* Fix compiler warnings in libpixelflingerAshok Bhat2014-02-203-42/+42
| | | | | Change-Id: I6a5708ae6bc934b196d59d81a6cd550b05ed704f Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
* pixelflinger: use __builtin___clear_cache instead of cacheflushColin Cross2014-02-111-5/+1
| | | | | | | cacheflush doesn't exist on LP64 any more, and gcc's __builtin___clear_cache is better in every way. Use it instead. Change-Id: Ibbf6facbdefc15b6dda51d014e1c44fb7aa2b17d
* system/core: rename aarch64 target to arm64Colin Cross2014-01-236-137/+137
| | | | | | | Rename aarch64 build targets to arm64. The gcc toolchain is still aarch64. Change-Id: Ia92d8a50824e5329cf00fd6f4f92eae112b7f3a3
* Pixelflinger: Add AArch64 support to pixelflinger JIT.Ashok Bhat2013-12-127-3/+1890
| | | | | | | | | | | | | | | | | See the comment-block at the top of Aarch64Assembler.cpp for overview on how AArch64 support has been implemented In addition, this commit contains [x] AArch64 inline asm versions of gglmul series of functions and a new unit test bench to test the functions [x] Assembly implementations of scanline_col32cb16blend and scanline_t32cb16blend for AArch64, with unit test bench Change-Id: I915cded9e1d39d9a2a70bf8a0394b8a0064d1eb4 Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
* Pixelflinger: Support for handling 64-bit addresses in GGL AssemblerAshok Bhat2013-12-127-19/+80
| | | | | | | | | | | | | | | | | | | | | | GGLAssembler assumes addresses to be 32-bit and uses ARM 32-bit instructions to load/store/manipulate addresses. To support, 64-bit architectures, following changes has been done 1. ARMAssemblerInterface has been extended to support four new operations ADDR_LDR, ADDR_STR, ADDR_SUB, ADDR_ADD. Base class implements these virtual functions to use 32bit equivalent function. This avoids existing 32-bit Assembler backend implementations like ARMAssembler and MIPSAssembler from mapping the new functions to existing equivalent routines. This also allows 64-bit Architectures like AArch64 to override the function in their assembler backend implementations. 2. GGLAssembler code (spread over GGLAssembler.cpp, GGLAssembler.h and texturing.cpp) has been changed to use the new operations for address operations. Change-Id: I3d7eace4691e3e47cef737d97ac67ce6ef4fb18d Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
* Pixelflinger: Fix issue of pointers being stored in intsAshok Bhat2013-12-121-3/+3
| | | | | | | | | | Pixelflinger's code makes assumptions, at certain places, that pointers can be stored as ints. This patch makes use of uintptr_t wherever pointers are stored as int or cast to int. Change-Id: Ie76f425cbc82ac038a747f77a95bd31774f4a8e8 Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
* move tinyutils into its own namespaceMathias Agopian2013-04-0124-23/+2361
| | | | | | | | | I was fed-up with the constant conflicts in Eclipse with the "libutils" version. Also fix a few copyright notices. Change-Id: I8ffcb845af4b5d0d178f5565f64dfcfbfa27fcd6
* Remove unnecessary compiler pragma.Ian Rogers2012-08-291-8/+3
| | | | | | | | | | With dlmalloc 2.8.6 the compiler pragmas to suppress warnings are not necessary. Also fix compiler warning about redefinition of LOG_TAG. Depends upon: https://android-review.googlesource.com/42351 Change-Id: I50f70be31f4bd994b09083e722759464476c70b3
* Merge "Add MIPS support to pixelflinger."Jean-Baptiste Queru2012-08-2716-179/+3935
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| * Add MIPS support to pixelflinger.Paul Lind2012-08-1316-179/+3935
| | | | | | | | | | | | | | See the comment-block at the top of MIPSAssembler.cpp for implementation overview. Change-Id: Id492c10610574af8c89c38d19e12fafc3652c28a
* | Upgrade to dlmalloc 2.8.5.Ian Rogers2012-08-202-26/+67
|/ | | | | | | | | | Remove mspace functionality from cutils. Directly declare mspace from dlmalloc in code flinger's code cache, and manage without using morecore. Depends upon: https://android-review.googlesource.com/41717 Change-Id: If927254febd4414212c690f16509ef2ee1b44b44
* Rename (IF_)LOGE(_IF) to (IF_)ALOGE(_IF) DO NOT MERGESteve Block2012-01-085-7/+7
| | | | | Bug: 5449033 Change-Id: Ibcffdcf620ebae1c389446ce8e9d908f11ac039c
* Rename (IF_)LOGI(_IF) to (IF_)ALOGI(_IF) DO NOT MERGESteve Block2012-01-041-1/+1
| | | | | Bug: 5449033 Change-Id: I4951baa981f09a84ce483e3d1bd0f9ebe009035f
* am 4906db21: Merge "codeflinger: Correct misleading comment of STM instruction"Jean-Baptiste Queru2010-11-231-1/+1
|\ | | | | | | | | * commit '4906db21e041327042b87122b233e1f150618334': codeflinger: Correct misleading comment of STM instruction
| * codeflinger: Correct misleading comment of STM instructionKan-Ru Chen2010-08-181-1/+1
| | | | | | | | | | | | | | | | According to the ARM Architecture Reference Manual, the comment on STM instruction should be in reverse order. Change-Id: I4af852a0478798ff7b02ab9c29c68e320ff78696 Signed-off-by: Kan-Ru Chen <kanru@0xlab.org>
* | am 8e0e372a: Set PROT_EXEC on the whole pixelflinger code cache.Jean-Baptiste Queru2010-10-151-1/+1
|\ \ | | | | | | | | | | | | | | | | | | Merge commit '8e0e372a388434a0553810e2b958e59a26a6bd96' into gingerbread-plus-aosp * commit '8e0e372a388434a0553810e2b958e59a26a6bd96': Set PROT_EXEC on the whole pixelflinger code cache.
| * | Set PROT_EXEC on the whole pixelflinger code cache.Jean-Baptiste Queru2010-10-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pointer difference between word pointers is a number of words, and it needs to be multiplied by the size of a word to get a proper byte size. Without this, we tend to see crashes when the code crosses a page boundary. Bug: 3026204 Bug: 3097482 Change-Id: I37776d26d5afcdb1da71680de02fbb95e6548371
* | | merge from froyo-plus-aospThe Android Open Source Project2010-06-217-1/+49
|\ \ \ | |/ / |/| / | |/ Change-Id: Ie231effb4d9dfd63aa98ec08b269c31ce32aa1c0
| * Fix build - cpu-features is ARM-specificJean-Baptiste Queru2010-06-151-0/+2
| | | | | | | | Change-Id: I66521f279545a249e3dcb645914f7b66f23cef21
| * Adds support for UBFX to JIT and DisassemblerMartyn Capewell2010-05-287-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces UBFX instruction generation abilities to the Pixelflinger JIT, and also modifies the component extraction function to generate the instruction. The extract function contains defines to prevent generation of UBFX on pre-v7 cores. The JIT itself retains the ability to produce the instruction even on v5/6. This patch only generates UBFX when MOV, AND or BIC can't be used. Based on the TRM, this appears to be faster on A9 than using UBFX in all cases. On startup, Pixelflinger JITs three chunks of code. UBFX improves these as follows: 00000077:03515104_00000000_00000000 (Blends a single colour into an RGB565 buffer.) Before: 27 inst/pixel, After: 24 inst/pixel, Improvement: 12.5% 00000077:03545404_00000A01_00000000 (Blends RGBA8888 texture into an RGB565 buffer using alpha.) Before: 30 inst/pixel, After: 27 inst/pixel, Improvement: 11.1% 00000077:03545404_00000A04_00000000 (Blends RGB565 texture into an RGB565 buffer using alpha.) Before: 29 inst/pixel, After: 27 inst/pixel, Improvement: 7.4%
* | Allow pixelflinger to work when NX (No Execute) is enabled.Nick Kralevich2010-05-072-7/+33
|/ | | | | | | | | | | | | Instead of allocating memory from the (non executable) heap, allocate memory using mspace and ensure that we use mprotect to mark it as PROT_EXEC. This allows pixelflinger to continue to work even when NX protections are enabled. Testing: Using the ApiDemos market app, verify that Apidemos -> Graphics -> OpenGL ES -> GLSurfaceView works when "adb shell setprop debug.egl.hw 0" is set. Change-Id: Ib569cd2543c6fa25688ee76325a712bc2347450b
* cpu-features.h is only available for ARMBruce Beare2010-05-041-1/+1
| | | | Change-Id: I1e8001a1875bfd9cebfe18dfd757556b55c8213c
* fix sim buildJean-Baptiste Queru2010-05-031-0/+2
| | | | Change-Id: Ide300eafbcbbc6dfae25fe86188302c6676c4a3b
* Fix LDM addressing mode disassemblyMartyn Capewell2010-04-291-1/+1
| | | | | | | | | | | | | | | | The Pixelflinger disassembler does not handle LDM addressing modes correctly, assuming that the P and U bits in the instruction mean the same in both LDM and STM. This results in the disassembler producing sequences like: stmfd r13!, {r4-r11, r14} ... ... ... ldmea r13!, {r4-r11, r14} This small patch fixes it by EORing the P and U bits with the Load/Store bit. Change-Id: Ic7a1556642c4e29415fc3697019f1239b6c26fc2
* Adds UXTB16 support to PixelflingerMartyn Capewell2009-12-077-1/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add support for UXTB16 to the disassembler * Add encoding of the UXTB16 instruction to the Pixelflinger JIT. Introducing the UXTB16 instruction allows removal of some masking code, and is beneficial from a pipeline point of view - lots of UXTB16 followed by MUL sequences. Also, further rescheduling and use of SMULWB brings extra performance improvements. * Use UXTB16 in bilinear filtered texturing Uses UXTB16 to extract channels for SIMD operations, rather than creating and ANDing with masks. Saves a register and is faster on A8, as UXTB16 result can feed into first stage of multiply, unlike AND. Also, used SMULWB rather than SMULBB, which allows removal of MOVs used to rescale results. Code has been scheduled for A8 pipeline, specifically aiming to allow multiplies to issue in pipeline 0, for efficient dual issue operation. Testing on SpriteMethodTest (http://code.google.com/p/apps-for-android/) gives 8% improvement (12.7 vs. 13.7 fps.) SMULBB to SMULWB trick could be used in <v6 code path, but this hasn't been implemented.
* eclair snapshotJean-Baptiste Queru2009-11-121-11/+1
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* fix 1650170 pixelflinger depends on KeyedVector.h, etcMathias Agopian2009-06-012-4/+4
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* auto import from //depot/cupcake/@135843The Android Open Source Project2009-03-0316-0/+6770
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* auto import from //depot/cupcake/@135843The Android Open Source Project2009-03-0316-6770/+0
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* auto import from //branches/cupcake/...@126645The Android Open Source Project2009-01-151-1/+1
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* Code drop from //branches/cupcake/...@124589The Android Open Source Project2008-12-175-25/+94
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* Initial ContributionThe Android Open Source Project2008-10-2116-0/+6701
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