| Commit message (Collapse) | Author | Age | Files | Lines |
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pixelflinger doesn't have to run on the Mac, but the Condition
code might.
Change-Id: Ib4e9b4daa6e848ffd5742959427b172d45f08e3c
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Intel accidentally made this dead code in 2010 with commit
2bef93cc20155c3a59cdbb22c564c4b385b2c160, and no one's ever noticed.
Since no one noticing for so long implies that it doesn't matter,
let's just kill the supposedly optimized code.
Change-Id: Id5b37056cb8884c20bfe2db362e19b46f02e337d
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Bug: 18556103
Change-Id: Ife07cf63948f1c248bcde5685cdb6d89c373d988
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More UD literals that weren't caught by hammerhead...
Change-Id: I6b0abdeef41d1f40c2fe86843b5149925ff6356e
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BUG: 18106835
Change-Id: Ic0051d5035e5684de0091cd3528d65e1b1e57161
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Later we will enable integrated-as as default at the global level.
BUG: 17820427
Change-Id: I1beed3e75d074d970fa9112ec1c0f0df3d43947a
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Use expected inline behavior with clang.
GCC defaults to -std=gnu90, giving C89 inline semantics with GNU
extensions. Clang defaults to C99. Explicitly use gnu90.
Mark an unused parameter as __unused.
Fix some incorrect casts.
Change-Id: I05b95585d5e3688eda71769b63b6b8a9237bcaf4
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Temporarily use generic C-coded libpixelflinger & memset on mips32r6.
Change-Id: I629b11ba955eaba323cba1df96c39f75f4d24d62
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This has the side effect of building tests for both 32
and 64 bit, where required.
Change-Id: I674800d34b4fa7cc5d34573c96b754ac85777970
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CodeCache casts base address to long and then adds size (of type
ssize_t) to get end address. This can cause sign-extension problems.
This patch instead uses simple pointer arithmetic.
Change-Id: Ib71d515a6fd6a7f4762cf974d6cf4eba9a601fa8
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
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For now, use generic C code instead of generated mips instructions,
in the same manner as used on x86 and x86_64 targets.
Change-Id: If3607484e0a446a755c62c030b3069d46ab5beb2
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Change-Id: I74422cfdba341fcd1a6235044700cf3986e853d0
Signed-off-by: Hurri Lu <jlu32@marvell.com>
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bootable/recovery has a dependent commit: I9adb470b04e4301989d128c9c3097b21b4dea431
Change-Id: Icf23e659265d71d5226d527c2b40cfbc132320ee
Signed-off-by: Sasha Levitskiy <sanek@google.com>
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ARCH_ARM_HAVE_NEON is only ever defined to true, so test for that.
For the NEON function to be used, the file has to include
machine/cpu-features.h so that __ARM_HAVE_NEON is defined.
Change-Id: I0db196b39c493092415859e009531fcff6fc1e8b
Signed-off-by: Kévin PETIT <kevin.petit@arm.com>
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The error condition was not correctly detected: an error was
reported by checking that the index returned by CodeCache::cache
was non-zero. This did not work because this function can return
a positive value on success.
Change-Id: I1f90125ee62ab277b80da4dfb341733cd6e8e86a
Signed-off-by: Kévin PETIT <kevin.petit@arm.com>
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Change-Id: I6a5708ae6bc934b196d59d81a6cd550b05ed704f
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
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Use the LOCAL_*_arch variables to support building for 32-bit and
64-bit at the same time.
Change-Id: Ibef8044e8b6500a6aa111320eb35bcdaf51ad064
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cacheflush doesn't exist on LP64 any more, and gcc's
__builtin___clear_cache is better in every way. Use it instead.
Change-Id: Ibbf6facbdefc15b6dda51d014e1c44fb7aa2b17d
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Bug: 12708004
Change-Id: I99f222b2db1d128abf6ffbf7173a5aaff48f8e85
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Rename aarch64 build targets to arm64. The gcc toolchain is still
aarch64.
Change-Id: Ia92d8a50824e5329cf00fd6f4f92eae112b7f3a3
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See the comment-block at the top of Aarch64Assembler.cpp
for overview on how AArch64 support has been implemented
In addition, this commit contains
[x] AArch64 inline asm versions of gglmul series of
functions and a new unit test bench to test the
functions
[x] Assembly implementations of scanline_col32cb16blend
and scanline_t32cb16blend for AArch64, with unit
test bench
Change-Id: I915cded9e1d39d9a2a70bf8a0394b8a0064d1eb4
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
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GGLAssembler assumes addresses to be 32-bit and uses ARM 32-bit
instructions to load/store/manipulate addresses. To support, 64-bit
architectures, following changes has been done
1. ARMAssemblerInterface has been extended to support four new
operations ADDR_LDR, ADDR_STR, ADDR_SUB, ADDR_ADD. Base class
implements these virtual functions to use 32bit equivalent
function. This avoids existing 32-bit Assembler backend
implementations like ARMAssembler and MIPSAssembler from
mapping the new functions to existing equivalent routines.
This also allows 64-bit Architectures like AArch64 to override
the function in their assembler backend implementations.
2. GGLAssembler code (spread over GGLAssembler.cpp, GGLAssembler.h
and texturing.cpp) has been changed to use the new operations
for address operations.
Change-Id: I3d7eace4691e3e47cef737d97ac67ce6ef4fb18d
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
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Pixelflinger's code makes assumptions, at certain places,
that pointers can be stored as ints. This patch makes use
of uintptr_t wherever pointers are stored as int or cast
to int.
Change-Id: Ie76f425cbc82ac038a747f77a95bd31774f4a8e8
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
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Avoiding the use of gnu extensions improves code portability
Change-Id: Ie9e94e3ce030f52a22997f8a48de1e6c1c549894
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Bug: 8580410
Change-Id: Iab3a9b4307f207c14a04a922cc7350c54e60e9ad
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I was fed-up with the constant conflicts in Eclipse
with the "libutils" version.
Also fix a few copyright notices.
Change-Id: I8ffcb845af4b5d0d178f5565f64dfcfbfa27fcd6
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With dlmalloc 2.8.6 the compiler pragmas to suppress warnings are not
necessary.
Also fix compiler warning about redefinition of LOG_TAG.
Depends upon: https://android-review.googlesource.com/42351
Change-Id: I50f70be31f4bd994b09083e722759464476c70b3
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See the comment-block at the top of MIPSAssembler.cpp for
implementation overview.
Change-Id: Id492c10610574af8c89c38d19e12fafc3652c28a
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Remove mspace functionality from cutils.
Directly declare mspace from dlmalloc in code flinger's code cache, and
manage without using morecore.
Depends upon: https://android-review.googlesource.com/41717
Change-Id: If927254febd4414212c690f16509ef2ee1b44b44
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Change-Id: Ib81cb01b8d90ed1afa1fd54b3cc009d7fec0f814
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Causes OpenGL Software Renderer to generate incorrect window
coordinates on MIPS & possibly x86
Change-Id: I3c51b6a5a4e6af75e9b31d9d47e4e4d894825888
Signed-off-by: Bhanu Chetlapalli <bhanu@mips.com>
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Change-Id: Iff15ac5e7ab226d437c08d23f18fd54e6793e65c
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Change-Id: I52fce957db06c281e2618daa4e2ecba19974f2eb
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Change-Id: I6c2a1d56dadb7e5c69e478f4d8c7d9f2127db2af
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Change-Id: I929ea38bc6fe6efeefa7870c8e7e4c19cd0029b3
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Change-Id: Ia0476219b71ece949595515ee07ea072ed349d73
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Change-Id: Ia9a357dec5ad12eea93fd03401a3b02b38e4e94f
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Change-Id: Ic107c60080e55e1f9092f20fe3bd55e7592ca9fd
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This patch adds a dozen more "shortcut" scanline-processing functions
to pixel-flingers. All of them avoid using the JIT for the corresponding
operation (on ARM), or using the generic and _extremely_ slow 'scanline'
function (on x86, where there is no JIT).
The shortcuts were selected by running the system under emulation
(build full_x86-eng, then launch emulator-x86), and correspond to
operations that are in use when using the system's typical UI features.
This makes it much more responsive and amenable to testing most
applications, at least those that don't use OpenGL ES heavily.
Note that HW OpenGLES emulation is under completion and should solve this
problem entirely, though is not there yet.
Change-Id: I9c73ba21ad158d6cc5532fabe7ed2419e00ecb3f
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* commit '4906db21e041327042b87122b233e1f150618334':
codeflinger: Correct misleading comment of STM instruction
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According to the ARM Architecture Reference Manual, the comment on
STM instruction should be in reverse order.
Change-Id: I4af852a0478798ff7b02ab9c29c68e320ff78696
Signed-off-by: Kan-Ru Chen <kanru@0xlab.org>
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Merge commit '8e0e372a388434a0553810e2b958e59a26a6bd96' into gingerbread-plus-aosp
* commit '8e0e372a388434a0553810e2b958e59a26a6bd96':
Set PROT_EXEC on the whole pixelflinger code cache.
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The pointer difference between word pointers is a number
of words, and it needs to be multiplied by the size of a word
to get a proper byte size.
Without this, we tend to see crashes when the code crosses
a page boundary.
Bug: 3026204
Bug: 3097482
Change-Id: I37776d26d5afcdb1da71680de02fbb95e6548371
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Change-Id: I849703a709fe4bf9ea7181268221d9b648b2e73d
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Change requested by Android Open Source Project
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Merge commit '5dfd90e5c79774d9981d25ab4defbd1e1f652c34' into gingerbread-plus-aosp
* commit '5dfd90e5c79774d9981d25ab4defbd1e1f652c34':
pixelflinger: Fix function naming typo: gglBitBlti
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From the functionality, the function gglBitBlti() implemented bit-block
(image) transfer operation in which several bitmaps are combined into
one using a raster operator. Renaming to gglBitBlit() should be
explicit.
Change-Id: I23886623b5421131cf7c7bfb8ec67c3809566c93
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