1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
|
/* libs/pixelflinger/codeflinger/ARMAssemblerInterface.h
**
** Copyright 2006, The Android Open Source Project
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.
** You may obtain a copy of the License at
**
** http://www.apache.org/licenses/LICENSE-2.0
**
** Unless required by applicable law or agreed to in writing, software
** distributed under the License is distributed on an "AS IS" BASIS,
** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
** See the License for the specific language governing permissions and
** limitations under the License.
*/
#ifndef ANDROID_ARMASSEMBLER_INTERFACE_H
#define ANDROID_ARMASSEMBLER_INTERFACE_H
#include <stdint.h>
#include <sys/types.h>
namespace android {
// ----------------------------------------------------------------------------
class ARMAssemblerInterface
{
public:
virtual ~ARMAssemblerInterface();
enum {
EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV,
HS = CS,
LO = CC
};
enum {
S = 1
};
enum {
LSL, LSR, ASR, ROR
};
enum {
ED, FD, EA, FA,
IB, IA, DB, DA
};
enum {
R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
SP = R13,
LR = R14,
PC = R15
};
enum {
#define LIST(rr) L##rr=1<<rr
LIST(R0), LIST(R1), LIST(R2), LIST(R3), LIST(R4), LIST(R5), LIST(R6),
LIST(R7), LIST(R8), LIST(R9), LIST(R10), LIST(R11), LIST(R12),
LIST(R13), LIST(R14), LIST(R15),
LIST(SP), LIST(LR), LIST(PC),
#undef LIST
LSAVED = LR4|LR5|LR6|LR7|LR8|LR9|LR10|LR11 | LLR
};
enum {
CODEGEN_ARCH_ARM = 1, CODEGEN_ARCH_MIPS
};
// -----------------------------------------------------------------------
// shifters and addressing modes
// -----------------------------------------------------------------------
// these static versions are used for initializers on LDxx/STxx below
static uint32_t __immed12_pre(int32_t immed12, int W=0);
static uint32_t __immed8_pre(int32_t immed12, int W=0);
virtual bool isValidImmediate(uint32_t immed) = 0;
virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm) = 0;
virtual uint32_t imm(uint32_t immediate) = 0;
virtual uint32_t reg_imm(int Rm, int type, uint32_t shift) = 0;
virtual uint32_t reg_rrx(int Rm) = 0;
virtual uint32_t reg_reg(int Rm, int type, int Rs) = 0;
// addressing modes...
// LDR(B)/STR(B)/PLD
// (immediate and Rm can be negative, which indicates U=0)
virtual uint32_t immed12_pre(int32_t immed12, int W=0) = 0;
virtual uint32_t immed12_post(int32_t immed12) = 0;
virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0) = 0;
virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0) = 0;
// LDRH/LDRSB/LDRSH/STRH
// (immediate and Rm can be negative, which indicates U=0)
virtual uint32_t immed8_pre(int32_t immed8, int W=0) = 0;
virtual uint32_t immed8_post(int32_t immed8) = 0;
virtual uint32_t reg_pre(int Rm, int W=0) = 0;
virtual uint32_t reg_post(int Rm) = 0;
// -----------------------------------------------------------------------
// basic instructions & code generation
// -----------------------------------------------------------------------
// generate the code
virtual void reset() = 0;
virtual int generate(const char* name) = 0;
virtual void disassemble(const char* name) = 0;
virtual int getCodegenArch() = 0;
// construct prolog and epilog
virtual void prolog() = 0;
virtual void epilog(uint32_t touched) = 0;
virtual void comment(const char* string) = 0;
// data processing...
enum {
opAND, opEOR, opSUB, opRSB, opADD, opADC, opSBC, opRSC,
opTST, opTEQ, opCMP, opCMN, opORR, opMOV, opBIC, opMVN
};
virtual void
dataProcessing( int opcode, int cc, int s,
int Rd, int Rn,
uint32_t Op2) = 0;
// multiply...
virtual void MLA(int cc, int s,
int Rd, int Rm, int Rs, int Rn) = 0;
virtual void MUL(int cc, int s,
int Rd, int Rm, int Rs) = 0;
virtual void UMULL(int cc, int s,
int RdLo, int RdHi, int Rm, int Rs) = 0;
virtual void UMUAL(int cc, int s,
int RdLo, int RdHi, int Rm, int Rs) = 0;
virtual void SMULL(int cc, int s,
int RdLo, int RdHi, int Rm, int Rs) = 0;
virtual void SMUAL(int cc, int s,
int RdLo, int RdHi, int Rm, int Rs) = 0;
// branches...
virtual void B(int cc, uint32_t* pc) = 0;
virtual void BL(int cc, uint32_t* pc) = 0;
virtual void BX(int cc, int Rn) = 0;
virtual void label(const char* theLabel) = 0;
virtual void B(int cc, const char* label) = 0;
virtual void BL(int cc, const char* label) = 0;
// valid only after generate() has been called
virtual uint32_t* pcForLabel(const char* label) = 0;
// data transfer...
virtual void LDR (int cc, int Rd,
int Rn, uint32_t offset = __immed12_pre(0)) = 0;
virtual void LDRB(int cc, int Rd,
int Rn, uint32_t offset = __immed12_pre(0)) = 0;
virtual void STR (int cc, int Rd,
int Rn, uint32_t offset = __immed12_pre(0)) = 0;
virtual void STRB(int cc, int Rd,
int Rn, uint32_t offset = __immed12_pre(0)) = 0;
virtual void LDRH (int cc, int Rd,
int Rn, uint32_t offset = __immed8_pre(0)) = 0;
virtual void LDRSB(int cc, int Rd,
int Rn, uint32_t offset = __immed8_pre(0)) = 0;
virtual void LDRSH(int cc, int Rd,
int Rn, uint32_t offset = __immed8_pre(0)) = 0;
virtual void STRH (int cc, int Rd,
int Rn, uint32_t offset = __immed8_pre(0)) = 0;
// block data transfer...
virtual void LDM(int cc, int dir,
int Rn, int W, uint32_t reg_list) = 0;
virtual void STM(int cc, int dir,
int Rn, int W, uint32_t reg_list) = 0;
// special...
virtual void SWP(int cc, int Rn, int Rd, int Rm) = 0;
virtual void SWPB(int cc, int Rn, int Rd, int Rm) = 0;
virtual void SWI(int cc, uint32_t comment) = 0;
// DSP instructions...
enum {
// B=0, T=1
// yx
xyBB = 0, // 0000,
xyTB = 2, // 0010,
xyBT = 4, // 0100,
xyTT = 6, // 0110,
yB = 0, // 0000,
yT = 4, // 0100
};
virtual void PLD(int Rn, uint32_t offset) = 0;
virtual void CLZ(int cc, int Rd, int Rm) = 0;
virtual void QADD(int cc, int Rd, int Rm, int Rn) = 0;
virtual void QDADD(int cc, int Rd, int Rm, int Rn) = 0;
virtual void QSUB(int cc, int Rd, int Rm, int Rn) = 0;
virtual void QDSUB(int cc, int Rd, int Rm, int Rn) = 0;
virtual void SMUL(int cc, int xy,
int Rd, int Rm, int Rs) = 0;
virtual void SMULW(int cc, int y,
int Rd, int Rm, int Rs) = 0;
virtual void SMLA(int cc, int xy,
int Rd, int Rm, int Rs, int Rn) = 0;
virtual void SMLAL(int cc, int xy,
int RdHi, int RdLo, int Rs, int Rm) = 0;
virtual void SMLAW(int cc, int y,
int Rd, int Rm, int Rs, int Rn) = 0;
// byte/half word extract...
virtual void UXTB16(int cc, int Rd, int Rm, int rotate) = 0;
// bit manipulation...
virtual void UBFX(int cc, int Rd, int Rn, int lsb, int width) = 0;
// -----------------------------------------------------------------------
// convenience...
// -----------------------------------------------------------------------
inline void
ADC(int cc, int s, int Rd, int Rn, uint32_t Op2) {
dataProcessing(opADC, cc, s, Rd, Rn, Op2);
}
inline void
ADD(int cc, int s, int Rd, int Rn, uint32_t Op2) {
dataProcessing(opADD, cc, s, Rd, Rn, Op2);
}
inline void
AND(int cc, int s, int Rd, int Rn, uint32_t Op2) {
dataProcessing(opAND, cc, s, Rd, Rn, Op2);
}
inline void
BIC(int cc, int s, int Rd, int Rn, uint32_t Op2) {
dataProcessing(opBIC, cc, s, Rd, Rn, Op2);
}
inline void
EOR(int cc, int s, int Rd, int Rn, uint32_t Op2) {
dataProcessing(opEOR, cc, s, Rd, Rn, Op2);
}
inline void
MOV(int cc, int s, int Rd, uint32_t Op2) {
dataProcessing(opMOV, cc, s, Rd, 0, Op2);
}
inline void
MVN(int cc, int s, int Rd, uint32_t Op2) {
dataProcessing(opMVN, cc, s, Rd, 0, Op2);
}
inline void
ORR(int cc, int s, int Rd, int Rn, uint32_t Op2) {
dataProcessing(opORR, cc, s, Rd, Rn, Op2);
}
inline void
RSB(int cc, int s, int Rd, int Rn, uint32_t Op2) {
dataProcessing(opRSB, cc, s, Rd, Rn, Op2);
}
inline void
RSC(int cc, int s, int Rd, int Rn, uint32_t Op2) {
dataProcessing(opRSC, cc, s, Rd, Rn, Op2);
}
inline void
SBC(int cc, int s, int Rd, int Rn, uint32_t Op2) {
dataProcessing(opSBC, cc, s, Rd, Rn, Op2);
}
inline void
SUB(int cc, int s, int Rd, int Rn, uint32_t Op2) {
dataProcessing(opSUB, cc, s, Rd, Rn, Op2);
}
inline void
TEQ(int cc, int Rn, uint32_t Op2) {
dataProcessing(opTEQ, cc, 1, 0, Rn, Op2);
}
inline void
TST(int cc, int Rn, uint32_t Op2) {
dataProcessing(opTST, cc, 1, 0, Rn, Op2);
}
inline void
CMP(int cc, int Rn, uint32_t Op2) {
dataProcessing(opCMP, cc, 1, 0, Rn, Op2);
}
inline void
CMN(int cc, int Rn, uint32_t Op2) {
dataProcessing(opCMN, cc, 1, 0, Rn, Op2);
}
inline void SMULBB(int cc, int Rd, int Rm, int Rs) {
SMUL(cc, xyBB, Rd, Rm, Rs); }
inline void SMULTB(int cc, int Rd, int Rm, int Rs) {
SMUL(cc, xyTB, Rd, Rm, Rs); }
inline void SMULBT(int cc, int Rd, int Rm, int Rs) {
SMUL(cc, xyBT, Rd, Rm, Rs); }
inline void SMULTT(int cc, int Rd, int Rm, int Rs) {
SMUL(cc, xyTT, Rd, Rm, Rs); }
inline void SMULWB(int cc, int Rd, int Rm, int Rs) {
SMULW(cc, yB, Rd, Rm, Rs); }
inline void SMULWT(int cc, int Rd, int Rm, int Rs) {
SMULW(cc, yT, Rd, Rm, Rs); }
inline void
SMLABB(int cc, int Rd, int Rm, int Rs, int Rn) {
SMLA(cc, xyBB, Rd, Rm, Rs, Rn); }
inline void
SMLATB(int cc, int Rd, int Rm, int Rs, int Rn) {
SMLA(cc, xyTB, Rd, Rm, Rs, Rn); }
inline void
SMLABT(int cc, int Rd, int Rm, int Rs, int Rn) {
SMLA(cc, xyBT, Rd, Rm, Rs, Rn); }
inline void
SMLATT(int cc, int Rd, int Rm, int Rs, int Rn) {
SMLA(cc, xyTT, Rd, Rm, Rs, Rn); }
inline void
SMLALBB(int cc, int RdHi, int RdLo, int Rs, int Rm) {
SMLAL(cc, xyBB, RdHi, RdLo, Rs, Rm); }
inline void
SMLALTB(int cc, int RdHi, int RdLo, int Rs, int Rm) {
SMLAL(cc, xyTB, RdHi, RdLo, Rs, Rm); }
inline void
SMLALBT(int cc, int RdHi, int RdLo, int Rs, int Rm) {
SMLAL(cc, xyBT, RdHi, RdLo, Rs, Rm); }
inline void
SMLALTT(int cc, int RdHi, int RdLo, int Rs, int Rm) {
SMLAL(cc, xyTT, RdHi, RdLo, Rs, Rm); }
inline void
SMLAWB(int cc, int Rd, int Rm, int Rs, int Rn) {
SMLAW(cc, yB, Rd, Rm, Rs, Rn); }
inline void
SMLAWT(int cc, int Rd, int Rm, int Rs, int Rn) {
SMLAW(cc, yT, Rd, Rm, Rs, Rn); }
};
}; // namespace android
#endif //ANDROID_ARMASSEMBLER_INTERFACE_H
|
