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-rw-r--r--binutils-2.24/include/opcode/mips.h25
1 files changed, 23 insertions, 2 deletions
diff --git a/binutils-2.24/include/opcode/mips.h b/binutils-2.24/include/opcode/mips.h
index 41d042f..672be82 100644
--- a/binutils-2.24/include/opcode/mips.h
+++ b/binutils-2.24/include/opcode/mips.h
@@ -426,7 +426,11 @@ enum mips_operand_type {
OP_SAME_RS_RT,
/* Described by mips_prev_operand. */
- OP_CHECK_PREV
+ OP_CHECK_PREV,
+
+ OP_MAPPED_STRING,
+
+ OP_MXU_STRIDE
};
/* Enumerates the types of MIPS register. */
@@ -473,7 +477,11 @@ enum mips_reg_operand_type {
OP_REG_MSA,
/* MSA control registers $0-$31. */
- OP_REG_MSA_CTRL
+ OP_REG_MSA_CTRL,
+
+ OP_REG_MXU,
+
+ OP_REG_MXU_GP
};
/* Base class for all operands. */
@@ -526,6 +534,12 @@ struct mips_mapped_int_operand
bfd_boolean print_hex;
};
+struct mips_mapped_string_operand
+{
+ struct mips_operand root;
+ const char ** strings;
+ int allow_constants;
+};
/* An operand that encodes the most significant bit position of a bitfield.
Given a bitfield that spans bits [MSB, LSB], some operands of this type
encode MSB directly while others encode MSB - LSB. Each operand of this
@@ -994,6 +1008,11 @@ struct mips_opcode
following), for quick reference when adding more:
"AB"
"abdstuvwxy"
+
+ Extension character sequences used so far ("`" followed by the
+ following), for quick reference when adding more:
+ "ABEIOPTRSU"
+ "abcdefgimopr"
*/
/* These are the bits which may be set in the pinfo field of an
@@ -1258,6 +1277,8 @@ static const unsigned int mips_isa_table[] = {
#define ASE_MSA64 0x00001000
/* eXtended Physical Address (XPA) Extension. */
#define ASE_XPA 0x00002000
+/* MXU Extension. */
+#define ASE_MXU 0x00004000
/* MIPS ISA defines, use instead of hardcoding ISA level. */